• Title/Summary/Keyword: 3D Packaging

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Expectation of Nanotechnology Applications in Packaging (나노기술 적용을 통한 포장 분야의 전망)

  • Kim, Jai-Neung;Lee, Youn-Suk
    • KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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    • v.12 no.1
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    • pp.27-34
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    • 2006
  • Nanotechnology is playing an increasingly important role in the development on most areas of science and technology. Because of its potential of providing novel performance at the nanoscale, the nanotechnology can influence a wide range of applications such as information, energy, environment and biology, all essential for socioeconomic development in the near future. In the packaging industry, the main applications of nanotechnology are (1) to enhance durability, (2) improve gas and oxygen barriers of raw materials for films and packaging, (3) create new functional sensors, and (4) lengthen shelf life for the packaged food quality and will also help in pharmaceuticals and cosmetics. Nanotechnology is growing in an international interactions which accelerate in science, education, and industrial R&D. Government, industries and the business sector in Korea have shown a strong ambition towards the development of nanotechnology for the future. Meanwhile, a strategic investment in packaging area is much smaller compared to supporting research and development (R&D) of various major research areas. This article were reviewed the status and trends of current packaging research and development activities using nanotechnology in Korea, USA, Japan, and other international nations.

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Overview of High Performance 3D-WLP

  • Kim, Eun-Kyung
    • Korean Journal of Materials Research
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    • v.17 no.7
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    • pp.347-351
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    • 2007
  • Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

Evaluation of 12nm Ti Layer for Low Temperature Cu-Cu Bonding (저온 Cu-Cu본딩을 위한 12nm 티타늄 박막 특성 분석)

  • Park, Seungmin;Kim, Yoonho;Kim, Sarah Eunkyung
    • Journal of the Microelectronics and Packaging Society
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    • v.28 no.3
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    • pp.9-15
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    • 2021
  • Miniaturization of semiconductor devices has recently faced a physical limitation. To overcome this, 3D packaging in which semiconductor devices are vertically stacked has been actively developed. 3D packaging requires three unit processes of TSV, wafer grinding, and bonding, and among these, copper bonding is becoming very important for high performance and fine-pitch in 3D packaging. In this study, the effects of Ti nanolayer on the antioxidation of copper surface and low-temperature Cu bonding was investigated. The diffusion rate of Ti into Cu is faster than Cu into Ti in the temperature ranging from room temperature to 200℃, which shows that the titanium nanolayer can be effective for low-temperature copper bonding. The 12nm-thick titanium layer was uniformly deposited on the copper surface, and the surface roughness (Rq) was lowered from 4.1 nm to 3.2 nm. Cu bonding using Ti nanolayer was carried out at 200℃ for 1 hour, and then annealing at the same temperature and time. The average shear strength measured after bonding was 13.2 MPa.

Fracture Mode Analysis with ISB Bonding Process Parameter for 3D Packaging (3차원 적층 패키지를 위한 ISB 본딩 공정의 파라미터에 따른 파괴모드 분석에 관한 연구)

  • Lee, Young-Kang;Lee, Jae-Hak;Song, Jun-Yeob;Kim, Hyoung-Joon
    • Journal of Welding and Joining
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    • v.31 no.6
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    • pp.77-83
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    • 2013
  • 3D packaging technology using TSV (Through Silicon Via)has been studied in the recent years to achieve higher performance, lower power consumption and smaller package size because electrical line is shorter electrical resistivity than any other packaging technology. To stack TSV chips vertically, reliable and robust bonding technology is required because mechanical stress and thermal stress cause fracture during the bonding process. Cu pillar/solder ${\mu}$-bump bonding process is usually to interconnect TSV chips vertically although it has weak shape to mechanical stress and thermal stress. In this study, we suggest Insert-Bump (ISB) bonding process newly to stack TSV chips. Through experiments, we tried to find optimal bonding conditions such as bonding temperature and bonding pressure. After ISB bonding, we observed microstructure of bump joint by SEM and then evaluated properties of bump joint by die shear test.

3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.2
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Current Status of Semiconductor and Microelectronic Packaging Technology Development in Korea

  • Sun, Yong-Bin
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2002.05a
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    • pp.1-6
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    • 2002
  • It is very important to foresee the main stream of technology development in the future. Packaging related manufacturers in equipment and materials focused their strength on products sharing big portion of world markets. As a result, domestic supply sources for packaging materials and equipment has been increased, but the manufacturer's capital and manpower is so limited to develop high technology machinery and high functional materials. The current status of packaging infrastructures in Korea is reviewed statistically. The hot issues in packaging arena are now in wafer level packaging, 3D packaging, and ultra-thin packaging. In addition, the recent advancement in microelectronics packaging technology is also covered.

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On-chip Decoupling Capacitor for Power Integrity (전력 무결성을 위한 온 칩 디커플링 커패시터)

  • Cho, Seungbum;Kim, Sarah Eunkyung
    • Journal of the Microelectronics and Packaging Society
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    • v.24 no.3
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    • pp.1-6
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    • 2017
  • As the performance and density of IC devices increase, especially the clock frequency increases, power grid network integrity problems become more challenging. To resolve these power integrity problems, the use of passive devices such as resistor, inductor, and capacitor is very important. To manage the power integrity with little noise or ripple, decoupling capacitors are essential in electronic packaging. The decoupling capacitors are classified into voltage regulator capacitor, board capacitor, package capacitor, and on-chip capacitor. For next generation packaging technologies such as 3D packaging or wafer level packaging on-chip MIM decoupling capacitor is the key element for power distribution and delivery management. This paper reviews the use and necessity of on-chip decoupling capacitor.

3D Printed Electronics Research Trend (3차원 인쇄기술을 이용한 전자소자 연구 동향)

  • Park, Yea-Seol;Lee Ju-Yong;Kang, Seung-Kyun
    • Journal of the Microelectronics and Packaging Society
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    • v.28 no.2
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    • pp.1-12
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    • 2021
  • 3D printing, which designs product in three dimensions, draws attention as a technology that will lead the future for it dramatically shortens time for production without assembly, no matter how complex the structure is. The paper studies the latest researches of 3D-printed electronics and introduces papers studied electronics components, power supply, circuit interconnection and 3D-printed PCBs' applications. 3D-printed electronics showed possibility to simplify facilities and personalize electric devices by providing one-stop printing process of electronic components, soldering, stacking, and even encapsulation.

V-Band filter using Multilayer MCM-D Technology (MCM-D 공정기술을 이용한 V-BAND FILTER 구현에 관한 연구)

  • Yoo Chan-Sei;Song Sang-Sub;Part Jong-Chul;Kang Nam-Kee;Cha Jong-Bum;Seo Kwang-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.9 s.351
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    • pp.64-68
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    • 2006
  • Novel system-on-package (SOP) - D technology to improve the mechanical and thermal properties of a MCM-D substrate was suggested. Based on this investigation, the two types of band pass filters for the V-band application with unique structure were designed and implemented using 2-metals, 3-BCB layers. The first type using distributed resonator had the insertion loss below 2.6 dB at 55 GHz and group delay was below 0.06 ns. For the second type with edge coupled structure, the insertion loss and group delay were 3 dB and 0.1 ns, respectively. Suggested MCM-D substrate with band pass filter can be used to evaluate mm-Wave system including flip-chip bonded MMIC.

A Study on the Design and Fabrication of RF Receiver Module for IMT-2000 Handset (IMT-2000단말기용 RF 수신모듈 설계 및 제작에 관한 연구)

  • 이규복;송희석;박종철
    • Journal of the Microelectronics and Packaging Society
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    • v.7 no.3
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    • pp.19-25
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    • 2000
  • In this paper, we describe RF receiver module for IMT-2000 handset with 5 MHz channel bandwidth. The fabricated RF receiver module consists of Low Noise Amplifier, RF SAW filter, Down-converter, If SAW filter, AGC and PLL Synthesizer. The NF and IIP3 of LNA is 0.8 dB, 3 dBm at 2.14 GHz, conversion gain of down-converter is 10 dB, dynamic range of AGC is 80 dB, and phase noise of PLL is -100 dBc at 100 kHz. The receiver sensitivity is -110 dBm, adjacent channel selectivity is 48 dBm.

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