• JSTS:Journal of Semiconductor Technology and Science
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• 제1권4호
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 C
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• pp.1972-1975
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• 2002

In this paper, we have proposed low temperature co-fired ceramic (LTCC) based packaging for RF MEMS devices. The packaging structure is designed and evaluated with 3D full field simulation. 50 ${\Omega}$ matched coplanar waveguide(CPW) transmission line is employed as the test vehicle to evaluate the performances of the proposed package structure. The line is encapsulated with the LTCC packaging lid and connected to the via feed line. To reduce the insertion loss due to the packaging lid, the cavity with via post is formed in the packaging lid. The performances of the package structure is simulated with the different cavity depth and via-to-via length. Simulation results show that the proposed package structure has reflection loss better than 20 dB and insertion loss lower than 0.1 dB from DC to 30 GHz with the cavity depth and via-to-via length of 300 ${\mu}m$ and 350 ${\mu}m$, respectively. To realize the designed package structure, the cavity patterning is tested using the sandblast of LTCC.

• 전자통신동향분석
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• 제35권2호
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• pp.89-103
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• 전자통신동향분석
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• 제35권2호
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• pp.120-136
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• 전자통신동향분석
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• 제35권2호
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• pp.104-119
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• 한국광학회지
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• 제18권4호
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• pp.235-240
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• 2007

본 논문에서는 10 Gbps급 데이터 전송을 위한 CPW(coplanar waveguide) 피드라인(feed-line)을 이용한 세라믹 스템(stem) 기반의 TO 패키지를 제안하였다. 기존의 금속 기반 TO 패키지에서 사용되는 실린더형 피드라인의 주파수 특성과 세라믹 패키지에서 사용되는 CPW 피드라인의 주파수 특성의 차이를 이론적으로 분석 비교하였다. 그리고 이들 패키지에 DFB 레이저다이오드(laser diode: LD)를 실장하여 측정된 3 dB 주파수 대역폭은 각각 3.5 GHz와 7.8 GHz로 사용된 패키지에 따라 큰 차이를 갖는 것을 밝혔다. 이러한 측정결과는 등가회로를 이용한 이론적인 계산결과와 잘 일치함도 확인하였다. 이상의 결과를 바탕으로 LD 광모듈의 주파수 특성을 개선하기 위한 방안으로 세라믹 재질의 비전도성 유전체를 스템으로 이용한 세라믹 스템 기반의 CPW 피드라인을 장착한 새로운 TO 패키지를 제안하였다. 제안된 패키지는 HFSS(high frequency structure simulator)를 이용하여 추출된 S 파라미터 값으로부터 기존의 금속 기반의 TO 패키지보다 월등히 넓은 주파수 특성을 얻을 수 있다는 것을 알 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.301-306
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• 2015

An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a $0.25{\mu}m$ GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the $3{\times}3-mm^2$ QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses ($S_{11}$ and $S_{22}$) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is $1.1{\times}0.9mm^2$. To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 춘계학술대회 논문집
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• pp.381-382
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• 2012

• 한국지능시스템학회논문지
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• 제22권6호
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• pp.694-699
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• 2012

반도체 검사 공정에 적용하기 위한 대시야 백색광간섭계(WSI ; White Light Scanning Interferometer)를 사용한 반도체 검사 결과를 본 논문에서 제시한다. 각 서브스트레이트에 있는 동일한 여러 범프에 대한 3D 데이터 반복성 측정 실험 결과를 제시한다. 각 서브스트레이트의 모든 범프에 대한 3D 데이터 반복성 측정 실험 결과를 제시한다. 반도체 검사 공정에서 3D 데이터 검사를 고속으로 달성하기 위해 대시야 백색광간섭계를 사용한 반도체 검사는 매우 중요한 의미를 갖는다. 인라인 고속 3D 데이터 검사기 개발에 본 논문이 크게 기여할 수 있다.

• 마이크로전자및패키징학회지
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• 제15권1호
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• pp.39-44
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• 2008

In this paper, fully embedded 2.4GHz WLAN band pass filter (BPF) was investigated into a multi-layered organic packaging substrate using high Q spiral stacked inductors and high Dk MIM capacitors for low cost RF System on Package (SOP) applications. The proposed 2.4GHz WLAN BPF was designed by modifying chebyshev second order filter circuit topology. It was comprised of two parallel LC resonators for obtaining two transmission zeros. It was designed by using 2D circuit and 3D EM simulators for finding out optimal geometries and verifying their applicability. It exhibited an insertion loss of max -1.7dB and return loss of min -l7dB. The two transmission zeros were observed at 1.85 and 6.7GHz, respectively. In the low frequency band of $1.8GHz{\sim}1.9GHz$, the stop band suppression of min -23dB was achieved. In the high frequency band of $4.1GHz{\sim}5.4GHz$, the stop band suppression of min -l8dB was obtained. It was the first embedded and the smallest one of the filters formed into the organic packaging substrate. It has a size of $2.2{\times}1.8{\times}0.77mm^3$.