• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.4
• /
• pp.216-231
• /
• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Proceedings of the KIEE Conference
• /
• 2002.07c
• /
• pp.1972-1975
• /
• 2002

In this paper, we have proposed low temperature co-fired ceramic (LTCC) based packaging for RF MEMS devices. The packaging structure is designed and evaluated with 3D full field simulation. 50 ${\Omega}$ matched coplanar waveguide(CPW) transmission line is employed as the test vehicle to evaluate the performances of the proposed package structure. The line is encapsulated with the LTCC packaging lid and connected to the via feed line. To reduce the insertion loss due to the packaging lid, the cavity with via post is formed in the packaging lid. The performances of the package structure is simulated with the different cavity depth and via-to-via length. Simulation results show that the proposed package structure has reflection loss better than 20 dB and insertion loss lower than 0.1 dB from DC to 30 GHz with the cavity depth and via-to-via length of 300 ${\mu}m$ and 350 ${\mu}m$, respectively. To realize the designed package structure, the cavity patterning is tested using the sandblast of LTCC.

• Electronics and Telecommunications Trends
• /
• v.35 no.2
• /
• pp.89-103
• /
• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Electronics and Telecommunications Trends
• /
• v.35 no.2
• /
• pp.120-136
• /
• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Electronics and Telecommunications Trends
• /
• v.35 no.2
• /
• pp.104-119
• /
• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• Korean Journal of Optics and Photonics
• /
• v.18 no.4
• /
• pp.235-240
• /
• 2007

A ceramic stem based TO package incorporating a coplanar waveguide feed-line has been proposed allowing for 10 Gbps grade data transmission. The frequency response of a cylindrical feed-line fer a conventional metal based TO package was first analyzed, and compared with that of the CPW feed-line used for a ceramic based package such as a butterfly package. For the case where a DFB LD chip is packaged to an LD module, the measured 3 dB frequency bandwidths for the conventional and proposed packages were 3.5 GHz and 7.8 GHz respectively, which agree well with the theoretical results obtained from the modeling based on the small signal equivalent circuits. Consequently, we proposed a novel ceramic based TO package with a CPW feed-line in ceramic material as a stem to improve the frequency characteristics of the conventional one. And, its performance was theoretically observed to confirm that the proposed package provides even wider frequency bandwidth compared to the conventional one.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.2
• /
• pp.301-306
• /
• 2015

An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a $0.25{\mu}m$ GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the $3{\times}3-mm^2$ QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses ($S_{11}$ and $S_{22}$) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is $1.1{\times}0.9mm^2$. To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2012.05a
• /
• pp.381-382
• /
• 2012

• Journal of the Korean Institute of Intelligent Systems
• /
• v.22 no.6
• /
• pp.694-699
• /
• 2012

In this paper, semiconductor package inspection results using white light interferometer with large F.O.V., in order to apply semiconductor product inspection process, are shown. Experimental 3D data repeatability test results for the same special bumps of each substrate are shown. Experimental 3D data repeatability test results for all the bumps in each substrate are also shown. Semiconductor package inspection using white light interferometer with large F.O.V. is very important for the fast 3D data inspection in semiconductor product inspection process. This paper is surely helpful for the development of in-line type fast 3D data inspection machine.

• Journal of the Microelectronics and Packaging Society
• /
• v.15 no.1
• /
• pp.39-44
• /
• 2008

In this paper, fully embedded 2.4GHz WLAN band pass filter (BPF) was investigated into a multi-layered organic packaging substrate using high Q spiral stacked inductors and high Dk MIM capacitors for low cost RF System on Package (SOP) applications. The proposed 2.4GHz WLAN BPF was designed by modifying chebyshev second order filter circuit topology. It was comprised of two parallel LC resonators for obtaining two transmission zeros. It was designed by using 2D circuit and 3D EM simulators for finding out optimal geometries and verifying their applicability. It exhibited an insertion loss of max -1.7dB and return loss of min -l7dB. The two transmission zeros were observed at 1.85 and 6.7GHz, respectively. In the low frequency band of $1.8GHz{\sim}1.9GHz$, the stop band suppression of min -23dB was achieved. In the high frequency band of $4.1GHz{\sim}5.4GHz$, the stop band suppression of min -l8dB was obtained. It was the first embedded and the smallest one of the filters formed into the organic packaging substrate. It has a size of $2.2{\times}1.8{\times}0.77mm^3$.