• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.253-256
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• 2009

This paper describes a core generator (FFT_Core_Gen) which generates Verilog HDL models of 8 different FFT/IFFT cores with $N=64{\times}2^k$($0{\leq}k{\leq}7$ for OFDM-based communication systems. The generated FFT/IFFT cores are based on in-place single memory architecture, and use a hybrid structure of radix-4 and radix-2 DIF algorithm to accommodate various FFT lengths. To achieve both memory reduction and the improved SQNR, a conditional scaling technique is adopted, which conditionally scales the intermediate results of each computational stage, and the internal data and twiddle factor has 14 bits. The generated FFT/IFFT cores have the SQNR of 58-dB for N=8,192 and 63-dB for N=64. The cores synthesized with a $0.35-{\mu}m$ CMOS standard cell library can operate with 75-MHz@3.3-V, and a 8,192-point FFT can be computed in $762.7-{\mu}s$, thus the cores satisfy the specifications of wireless LAN, DMB, and DVB systems.

• Proceedings of the Korean Society of Surveying, Geodesy, Photogrammetry, and Cartography Conference
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• 2006.04a
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• pp.235-241
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• 2006

The demand of 3D terrain mapping techniques is increasing in many application fields such as CNS(Car Navigation System), web service system, DMB(Digital Multimedia Broadcasting) systems and etc To construct a 3D terrain map, it is a pre-requite step that register data collected from different surveying sources. This Paper Present the methodology to register airborne photo, LIDAR data, and digital map, which are major data sources to create a 3D terrain mao. For this purpose, we developed the generally applicable algorithm that uses linear features to register airborne photos and digital maps to LIDAR data. The algorithm explicitly formulates step-by-step methodologies to establish observation equations for transformation. The results clearly demonstrate the proposed algorithm is appropriate to register these data sources.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2010.04a
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• pp.151-153
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• 2010

In this paper, the tri-band planar monopole microstrip antenna which stimulaneously meets the three bands such as TRS, WLAN and DMB is designed. The designed antenna size was smaller using CPW-fed structure that shows a ground-plane and a patch-plane are existed at one layer. The proposed antenna is designed on FR-4 substrate with a relative dielectric constant 4.3, thickness of 1.5mm and tangent loss 0.04. The designed antenna shows that VSWR is below 2 and has good return loss below -10dB over the three bandwidths.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.07a
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• pp.381-384
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• 2011

DMB 와 같은 모바일 기기에서 3 차원 입체 영상 서비스를 제공하기 위해서는 스테레오스코픽 콘텐츠를 생성하는 단계에서 모바일 기기의 특성, 즉 3D 디스플레이의 특성을 고려하여 촬영하거나 또는 가공하여야 한다. 본 논문에서는 일반적으로 HD 급 고해상도로 촬영된 스테레오스코픽 3 차원 콘텐츠를 모바일 환경에 적합하도록 크기를 변환하기 위한 알고리즘 및 그에 따라 변환된 모바일 3 차원 영상의 분석 결과를 제시하고자 한다.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1638-1639
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• 2011

본 논문에서는 초소형 무선 USB 동글 장치를 위한 광대역 접힌(folded) 모노폴 안테나를 제안하였다. 제안된 안테나는 CPW 급전으로부터 삼지창 형상의 선로를 적용하여 광대역 특성을 구현하였다. 최종 설계된 안테나의 크기는 $16{\times}44.8{\times}3.5\;mm^3$이며, low-profile의 무선 USB 동글용 안테나에 적합하다. 제안된 안테나는 $S_{11}$ < -10 dB 기준으로 2.28~10.8 GHz의 공진 주파수 대역을 가지므로 WiBro (2.3~2.4 GHz), Bluetooth (2.4~2.484 GHz), WiMAX (2.5~2.7 GHz, 3.4~3.6 GHz), satellite DMB (2.605~2.655 GHz), 802.11b/g/a WLAN (2.4~2.485 GHz, 5.15~5.825 GHz), UWB(3.1~10.6 GHz)의 무선 대역을 지원 할 수 있다. 측정된 평균 이득의 범위는 -3.41 dBi 에서 -0.84 dBi 이다.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.6
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• pp.63-69
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• 2008

Reconfigurable RF one-chip solutions have been researched with the objective of designing for smaller-sized and more economical RF transceiver and it can be applied to a vehicular wireless terminal. The proposed voltage-controlled oscillator satisfies the targeted frequency range ($4.2{\sim}5.4\;GHz$) and the frequency planning which correspond to the standards such as CDMA(IS-95), PCS, GSM850, EGSM, WCDMA, WLAN, Bluetooth, WiBro, S-DMB, DSRC, GPS, and DVB-H/DMB-H/L(L Band). In order to improve phase noise performance, PMOS is adopted in the cross-coupled pair, the tail current source and MOS varactor in this VCO and differential-typed switching is proposed in capacitor array. Based on the measurement results, a total power dissipation is $5.3{\sim}6.0\;mW$ at 1.8 V power supply voltage. The oscillator is tuned from 4.05 to 5.62 GHz; The tuning range is 33%. The phase noise is -117.16 dBc/Hz at 1 MHz offset frequency and the FOM (Figure Of Merit) is $-180.84{\sim}-180.5$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.5 s.96
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• pp.541-548
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• 2005

The research deals with the prediction and the measurement of electromagnetic wave propagation in rectangular shaped tunnels at f=2.65 GHz. The received power level was measured in the straight and the curved tunnel by using a spectrum analyzer and Satellite DMB mobile phone. Thus we have gotten the data for two cases, the straight and the curved tunnel whose radius is 300m. In addition, the prediction of wave propagation was conducted based on the ray-launching method, in same tunnel where measurement was performed. A good agreement of the measured and the predicted path loss could be confirmed. The measured path loss shows a marked difference in propagation loss: the path-loss exponent, 3.21, and 3.98, for a straight and a curved tunnel, respectively. The reason that path-loss exponent is high in a curved tunnel is that there is no direct wave but only the reflected waves, which attenuates rapidly with distance due to multiple reflections. Also the predicted path loss shows path loss exeponent, 3.2 and 3.95, for a straight and a curved tunnel which are similar to the simulation results.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2005.11a
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• pp.633-636
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• 2005

최근의 전자기기는 소형, 경량화가 가속화되고 있고, 특히 휴대용 기기에서의 MP3, MOD, VOD, DMB, 3D 게임, 등 다양한 멀티미디어 콘텐츠에 대한 일반인의 접근성이 확대됨에 따라 휴대용 기기에서의 입체음향 효과에 대한 사용자의 관심이 고조되고 있다. 하지만, 휴대용 기기에서의 입체음향 효과 구현은 PC 환경에서의 구현과는 다르게, 적은 CPU 점유율, 작은 메모리 사용, 등 열악한 재생환경에서의 구현이 필요해, 기대만큼의 성능을 내기가 쉽지 않다. 이러한 제약된 환경에서 만족스러운 입체음향 효과의 구현을 위해서는 기기별 H/W 특성을 감안한 알고리듬 최적화가 필수이다. 본 논문에서는 휴대용 기기 환경에 최적화된 입체음향 기술과 동향, 국내에서 상용화된 XEN$^{TM}$ 솔루션에 대해 살펴봄으로서 향후 휴대용 기기를 위한 입체음향 기술개발 방향을 제시하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.72-76
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• 2008

In this paper, the several printed square loop antennas which modified monopole antennas are proposed. The proposed antennas are reduced about 20% physical size of antenna and miniaturized reactance value of impedance due to fold center part of the loop. They obtained omni-directional radiation patterns with broad bandwidth and feed method used coplanar waveguide to composed single planar. The proposed antenna bandwidth is about 900MHz($2.63{\sim}3.56GHz]$) resonance frequency on $VSWR{\le}2$. it can be sufficiency of S-DMB band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.