• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.201-202
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• 2012

This paper presents a simple and cost-effective stand-alone rapid battery charging system of 30kW for electric vehicles. The proposed system mainly consists of active front-end rectifier of neutral point clamped 3-level type and non-isolated bi-directional dc-dc converter of multi-phase interleaved half-bridge topology. The charging system is designed to operate for both lithium-polymer and lithium-ion batteries. The complete charging sequence is made up of three sub-interval operating modes; pre-charging mode, constant-current mode, and constant-voltage mode. Each mode is operated according to battery states: voltage, current and State of Charging (SOC). The proposed system is able to reach the full-charge state within less than 16min for the battery capacity of 8kWh by supplying the charging current of 67A. The optimal discharging algorithm for Vehicle to the Grid (V2G) operation has been adopted to maintain the discharging current of 1C. Owing to the simple and compact power conversion scheme, the proposed solution has superior module-friendly mechanical structure which is absolutely required to realize flexible power expansion capability in a very high-current rapid charging system. Experiment waveforms confirm the proposed functionality of the charging system.

• Journal of Biomedical Engineering Research
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• v.28 no.3
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• pp.429-440
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• 2007

A coded excitation has been studied to improve the performance for ultrasound imaging in term of SNR, imaging frame rate, contrast to tissue ratio, and so forth. However, it requires a complicated arbitrary waveform transmitter for each active channel that is typically composed of a multi-bit Digital-to-Analog Converter (DAC) and a linear power amplifier (LPA). Not only does the LPA increase the cost and size of a transmitter block, but it consumes much power, increasing the system complexity further and causing a heating-up problem. This paper proposes an optimized 1.5bit fourth order sigma-delta modulation technique applicable to design an efficient arbitrary waveform generator with greatly reduced power dissipation and hardware. The proposed SDM can provide a required SQNR with a low over-sampling ratio of 4. To this end, the loop coefficients are optimized to minimize the quantization noise power in signal band while maintaining system stability. In addition, the decision level for the 1.5 bit quantizer is optimized for a given input waveform, which results in the SQNR improvement of more than 5dB. Computer simulation results show that the SQNR of a FM(frequency modulated) signal generated by using the proposed method is about 26dB, and the peak side-lobe level (PSL) of its compressed waveform on receive is -48dB.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.3
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• pp.25-30
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• 2014

This paper describes the design of gate driver circuits in distributed maximum power point tracking(DMPPT) controller for photovoltaic system. For the effective DMPPT control in the existence of shadowed modules, high voltage gate driver is applied to drive the DC-DC converter in each module. Some analog blocks such as 12-b ADC, PLL, and gate driver are integrated in the SoC for DMPPT. To reduce the power consumption and to avoid the high voltage damage, a short pulse generator is added in the high side level shifter. The circuit was implemented with BCDMOS 0.35um technology and can support the maximum current of 2A and the maximum voltage of 50V.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.2
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• pp.233-238
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• 2018

This paper proposes a seamless MPPT operation mode transfer method of photovoltaic system. The photovoltaic system consists of a DC-DC boost converter, a DC-Link, and a 3-level neutral point clamp (NPC) type inverter. The PV voltage fluctuates due to the output characteristics of the solar pane1 depending on the irradiation amount and the temperature. The photovoltaic system requires seamless MPPT mode transfer method that the discontinuity does not occur in order to supply the stable power to system without affecting the fluctuation of the PV voltage. MPPT operation is divided into two modes by the voltage reference. Under the condition that the PV voltage is below 650V, the DC-DC boost converter performs MPPT through duty control based on perturb & observe (P&O) method, and the inverter conducts DC-link voltage and grid current controls in synchronous reference frame. On the other hand, when the PV voltage exceeds above 650V, inverter performs MPPT in accordance with the variation of DC-link voltage control while the converter stops operating. Two MPPT operation modes is smoothly transferred through the proposed method that DC-link voltage or grid current commands are appropriately adjusted from the certain criteria. The feasibility of the MPPT operation mode transfer method is verified using a 10kW solar photovoltaic system, experimental results have good performances that the fluctuation of PV current is reduced to 100%.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

• Progress in Superconductivity and Cryogenics
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• v.14 no.4
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• pp.36-40
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• 2012

This paper presents an experimental and numerical study on current limiting characteristics of a fault current controller (FCC). The FCC consists of an AC/DC power converter, a superconducting coil, and a control unit. Even though some previous researches proved that the FCC could adjust the fault current level, the current limiting characteristics by the superconducting coil should be investigated for design of the coil. In this paper, four kinds of model coils were tested; 1) air core, 2) iron core without any bias, 3) reversely magnetized core (RMC) using permanent magnets, and 4) RMC using an electromagnet. Based on a comparative study, it is confirmed that a RMC by an electromagnet (EM) could increase the effective inductance of the coil. In this paper, a numerical code to simulate the HTS coil with RMC was developed. This code can be applied to design the HTS coil with active reversely magnetized bias coil.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.14-23
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• 2010

This paper reports the fabrication of a DVB-T/H System in Package (SiP) that is able to receive and process the DVB-T/H signal. The DVB-T/H is the European telecommunication standard for Digital Video Broadcasting (DVB). An IC-embedded Printed Circuit Board (PCB) process, interpose a chip between PCB layers, has applied to the DVB-T/H SiP. The chip inserted in DVB-T/H SiP is the System on Chip (SoC) for mobile TV. It is comprised of a RF block for DVB-T/H RF signal and a digital block to convert received signal to digital signal for an application processor. To operate the DVB-T/H IC, a 3MHz DC-DC converter and LDO are on the DVB-T/H SiP. And a 38.4MHz crystal is used as a clock source. The fabricated DVB-T/H SiP form 4 layers which size is $8mm{\times}8mm$. The DVB-T/H IC is located between 2nd and 3rd layer. According to the result of simulation, the RF signal sensitivity is improved since the layout modification of the ground plane and via. And we confirmed the adjustment of LC value on power transmission is necessary to turn down the noise level in a SiP. Although the size of a DVB-T/H SiP is decreased over 70% than reference module, the power consumption and efficiency is on a par with reference module. The average power consumption is 297mW and the efficiency is 87%. But, the RF signal sensitivity is declined by average 3.8dB. This is caused by the decrease of the RF signal sensitivity which is 2.8dB, because of the noise from the DC-DC converter.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.57-60
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• 2004

This paper presents multibit Sigma-Delta ADC using Leslie-Singh Structure to Improve nonlinearity of feedback loop. 4-bit flash ADC for multibit Quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. Thus a Sigma-Delta ADC usually adds the dynamic element matching digital circuit within feedback loop. It occurs complexity of Sigma-Delta Circuit and increase of power dissipation. In this paper using the Leslie-Singh Structure for improving nonliearity of ADC. This structure operate at low oversampling ratio but is difficult to achieve high resolution. So in this paper propose improving loop filter for single-bit feedback multi-bit quantization Sigma-Delta ADC. It obtained 94.3dB signal to noise ratio over 615kHz bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is fabricated in 0.25um CMOS technology with 2.5V supply voltage.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.3
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• pp.129-134
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• 2020

Moisture infiltration inside the solar cell module, filling of EVA sheet, melting of the frame seal, and deterioration of power generation performance in the module one year after installation are occurring. Whitening phenomenon, electrode corrosion phenomenon, and dielectric breakdown phenomenon are appearing in solar cell module installed in Korea before 5-7 years, leading to deterioration of power generation performance, and big problems for long-term reliability and long life technology are emerging. Therefore, in order to solve these problems, the development of a micro inverter (MiCrco Inverter Converter, MiC) including the function of securing the durability of the solar cell module and monitoring the aging progress and the solar cell based on the monitoring data from the MiC smart monitoring programs have been proposed to determine the aging of modules. In addition, in order to become a highly efficient solar smart monitoring system through systematic operation management through IT convergence with MiC that has enhanced monitoring function of solar cell module, SoC(System On Chip) in micro inverter is the environment for solar cell module. There is a demand for functions that can detect information in a complex manner and perform communication and control when necessary. Based on these requirements, this paper aims to develop SoC-based low-cost MiC smart photovoltaic system technology.

• Journal of electromagnetic engineering and science
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• v.3 no.2
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• pp.86-90
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• 2003

A flat conversion loss in microwave mixer is hard to achieve if integrating with an image rejection filter(IRF). This is due to the change of termination condition with respect to the LO and IF frequency at RF port where the filter has 50 ohm termination property only in the RF band. This paper describes a flatness maintenance in the down mixer concerning a diode matching condition as well as an electrical length of embedding line at RF port. The implemented single balance diode mixer is suitable for a 23 ㎓ European Terrestrial Radio. RF, LO and fixed IF frequency chosen in this paper are 21.2∼22.4 ㎓, 22.4∼23.6 ㎓ and 1.2 ㎓, respectively. The measured results show a conversion loss of 8.5 ㏈, flatness of 1.2 ㏈ p-p, input P1㏈ of 7㏈m, IIP3 of 15.42 ㏈m with nominal LO power level of 10㏈m. The return loss of RF and LO port are less than - 15 ㏈ and - 12 ㏈, respectively and IF port is less than - 6 ㏈. LO/RF and LO/IF isolation are 18 ㏈ and 50 ㏈, respectively. This approach would be a helpful reference for designing up/down converter possessing a filtering element.