• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.857-863
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• 2014

In this work, we introduce various bonding technologies for 3D package and suggest Insert-Bump bonding (ISB) process newly to stack multi-layer chips successively. Microstructure of Insert-Bump bonding (ISB) specimens is investigated with respect to bonding parameters. Through experiments, we study on find optimal bonding conditions such as bonding temperature and bonding pressure and also evaluate in the case of fluxing and no-fluxing condition. Although no-fluxing bonding process is applied to ISB bonding process, good bonding interface at $270^{\circ}C$ is formed due to the effect of oxide layer breakage.

• Electronics and Telecommunications Trends
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• v.25 no.5
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• pp.97-105
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• 2010

모바일과 유비쿼터스 센서 네트워크 센서 시대가 도래함에 따라 가볍고, 작고, 얇고, 멀티기능을 구현할 수 있는 부품에 대한 요구가 증대하고 있다. 이에 대한 여러 가지 솔루션 중 MCM의 개념을 수직 방향으로 확장시킨 3D IC가 최근 각광을 받고 있다. 이는 물리적인 한계에 부딪힌 반도체 집적 공정의 한계를 극복하여 지속적으로 무어의 법칙에 맞춰 집적도를 향상시킬 수 있을 뿐만 아니라 소재와 공정이 달라도 3차원적으로 집적이 가능하여 메모리와 프로세서로 대표되는 디지털 칩뿐만 아니라 아날로그/RF, 수동소자, 전력소자, 센서/액추에이터, 바이오칩 등을 하나로 패키징 할 수 있는 장점이 있기 때문이다. 이를 통해 성능 향상, 경박단소, 저비용의 부품 개발이 가능하기 때문에 미국, 유럽, 일본 등 선도국뿐만 아니라 싱가포르, 타이완, 중국 등에서도 활발한 연구가 진행되고 있으며 CMOS 이미지 센서 모듈 생산에 TSV 기술이 이미 적용되고 있다. 본 고에서는 3D IC를 위한 TSV 및 적층 요소 기술을 소개하고 이를 통해 개발된 사례와 표준화 동향에 대하여 소개하고자 한다.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.25-32
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• 2012

Package for artificial satellite is to produce mass production for high package with reliability certification as well as develop SDRAM (synchronous dynamic RAM) module which has such as miniaturization, mass storage, and high reliability in space environment. It requires sophisticated technology with chip stacking or package stacking in order to increase up to 4Gbits or more for mass storage with space technology. To make it better, we should secure suitable processes by doing design, manufacture, and debugging. Pin type PCB substrate was then applied to QFP-Pin type 3D memory package fabrication. These results show that the 3D memory package for artificial satellite scheme is a promising candidate for the realization of our own domestic technologies.

• Proceedings of the KWS Conference
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• 2006.10a
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• pp.190-192
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• 2006

The 3-dimensional(3D) chip stacking technology is one of the leading technologies to realize a high density and high performance system in package(SIP). It could be found that it is the advanced process of through-hole via formation with the minimum damaged on the Si-wafer. Laser ablation is very effective method to penetrate through hole on the Si-wafer because it has the advantage that formed under $100{\mu}m$ diameter through-hole via without using a mask. In this paper, we studied the optimum method for a formation of through-hole via using femto-second laser heat sources. Furthermore, the processing parameters of the specimens were several conditions such as power of output, pulse repetition rate as well as irradiation method and time. And also the through-hole via form could be investigated and analyzed by microscope and analyzer.

• Journal of the Korean Society for Precision Engineering
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• v.26 no.12
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• pp.9-17
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• 2009

• Journal of the Microelectronics and Packaging Society
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• v.30 no.1
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• pp.1-16
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• 2023

Recently, the shift to next-generation wide-bandgap (WBG) power semiconductor for electric vehicle is accelerated due to the need to improve power conversion efficiency and to overcome the limitation of conventional Si power semiconductor. With the adoption of WBG semiconductor, it is also required that the packaging materials for power modules have high temperature durability. As an alternative to conventional high-temperature Pb-based solder, Ag sintering die attach, which is one of the power module packaging process, is receiving attention. In this study, we will introduce the recent research trends on the Ag sintering die attach process. The effects of sintering parameters on the bonding properties and methodology on the exact physical properties of Ag sintered layer by the realization 3D image are discussed. In addition, trends in thermal shock and power cycle reliability test results for power module are discussed.

• Journal of the Korean Society for Precision Engineering
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• v.17 no.7
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• pp.45-51
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• 2000

지난 세기부터 MEMS 제작 기술을 이용하여 만들어진 시스템들을 의학이나 생물학적인 용도로 응용하기 위한 많은 연구가 활발히 이루어져 왔다. 기술적인 측면에서 이러한 연구들은 MEMS 분야의 초창기에 강조되어 온 표면 및 몸체 미세 가공 기술(surface ＆ bulk micromachining)과 같은 미세 구조물 제작 기술의 발전에 힘입은 바 크다. 그러나 MEMS 기술이 점차 발전되어 오면서, 가공 기술이 고도화되고 미세 시스템의 구조가 점차 복잡해짐에 따라, 많은 연구들이 단순한 가공기술을 넘어 미세 시스템을 조립하고 집적화할 수 있는 기술, 접합 (bonding) 기술, 패키징 (packaging) 기술, 3차원 형상의 제작 기술, 실리콘(silicon)이나 유리(glass)가 아닌 다른 재료를 이용한 미세 가공 기술 등의 개발을 중심으로 이루어지고 있다.(중략)

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.1-6
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• 2010

This study presents the preform injection molding and the blow molding of the injection stretch-blow molding process for PET bottles. The numerical analysis of the injection molding and the blow molding of a preform is considered in this paper using CAE with a view to minimize the warpage and the thickness. In order to determine the design parameters and processing conditions in injection/blow molding, it is very important to establish the numerical model with physical phenomenon. In this study, a three dimensional model has been introduced for the purpose and flow simulations of filling, post-filling and cooling process are carried out. The simulations resulted in the warpage in good agreement with the measurements. Also, from the result of numerical analysis, we appropriately predicted the warpage, deformation and thickness distribution along the product walls.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.89-93
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• 2020

Complex warpage behavior of the electronic packages causes internal stress so many kinds of mechanical failure occur such as delamination or crack. Efforts to predict the warpage behavior accurately in order to prevent the decrease in yield have been approached from various aspects. For warpage prediction, silicon is generally treated as a homogeneous material, therefore it is described as showing no warpage behavior due to thermal loading. However, it was reported that warpage is actually caused by residual stress accumulated during grinding and polishing in order to make silicon wafer thinner, which make silicon wafer inhomogeneous through thickness direction. In this paper, warpage behavior of the single-side polished wafer at solder reflow temperature, the highest temperature in packaging processes, was measured using 3D digital image correlation (DIC) method. Mechanism was verified by measuring coefficient of thermal expansion (CTE) of both mirror-polished surface and rough surface.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.29-34
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• 2008

Generally, for conventional 3-D Hall sensor it is general that the sensitivity for $B_z$ is about 1/10 compared with those for $B_x$ or $B_y$. Therefore, in this work, we proposed 3-D Hall sensor with new structures. We have increased the sensitivity about 6 times to form the trench using anisotropic etching. And we have increased the sensitivity for the $B_z$ by 80 % compared with those of $B_x$ and $B_y$ using deposition of the ferromagnetic thin films on the bottom surface of the wafer to concentrate the magnetic fluxes. Sensitivities of the fabricated sensor with Ni/Fe film for $B_x,\;B_y$, and $B_z$ were measured as 361mV/T, 335mV/T, and 286mV/T, respectively. It has also showed sine wave of Hall voltages over a $360^{\circ}$ rotation. A packaged sensing part was $1.2{\times}1.2mm^2$. The measured linearity of the sensor was within ${\pm}3%$ of error. Resolution of the fabricated sensor was measured by $1{\times}10^{-5}T$.