• The Journal of Natural Sciences
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• v.7
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• pp.27-35
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• 1995

This paper introduces a VLSI (Very Large Scale Integrated Circuit) implementation of the 2-D Discrete Cosine Transform (DCT) with an application to image and video coding. This implementation, which is based upon a state space model, uses both algorithm and data partitioning to achieve high efficiency. With this implementation, the amount of data transfers between the processing elements (PEs) are reduced and all the data transfers are limitted to be local. This system accepts the input as a progressively scanned data stream which reduces the hardware required for the input data control module. With proper ordering of computations, a matrix transposition between two matrix by matrix multiplications, which is required in many 2-D DCT systems based upon a row-column decomposition, can be also removed. The new implementation scheme makes it feasible to implement a single 2-D DCT VLSI chip which can be easily expanded for a larger 2-D DCT by cascading these chips.

• Composites Research
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• v.35 no.5
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• pp.317-321
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• 2022

In this study, the PIC design method with machine learning that automatically assigning different stacking sequences according to loading types was applied bumper beam. The input value and labels of the training data for applying machine learning were defined as coordinates and loading types of reference elements that are part of the total elements, respectively. In order to compare the 2D and 3D implementation method, which are methods of representing coordinate value, training data were generated, and machine learning models were trained with each method. The 2D implementation method is divided FE model into each face and generating learning data and training machine learning models accordingly. The 3D implementation method is training one machine learning model by generating training data from the entire finite element model. The hyperparameter were tuned to optimal values through the Bayesian algorithm, and the k-NN classification method showed the highest prediction rate and AUC-ROC among the tuned models. The 3D implementation method revealed higher performance than the 2D implementation method. The loading type data predicted through the machine learning model were mapped to the finite element model and comparatively verified through FE analysis. It was found that 3D implementation PIC bumper beam was superior to 2D implementation and uni-stacking sequence composite bumper.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.183-192
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• 1999

The derivative equation measured of a ${\Delta}MV=Kp*{(EVn-EVn-1)+\frac{1}{Ki/S}* EVn+(Kd/S)*(2PVn-1-PVn-PVn-1)}$ is used on the machine apparatus of industrial field, but this par doesn\`t able to educate now, because we didn\`t have the implementation device of PID module, so the principle implementation system of the PID Module is manufactured and developed. Through this system, the implementation system of PID Module is practiced with that the SV and the set of P, I, D is set on the derivative equation measured of PID. A things to be known of this experiment result is flow. 1)PID module is known that had to be used with the module of A/D and D/A. 2) In process of PV is approached to the SV to follow Kp, Ti and Td to cause a constant of set value on the $MVp=Kp*EV, MV=\frac{1}{Ki}{\int}EVdt, MVd=Td\frac{d}{dt}EV$, the variable rate of E and Kp, Td, Ti in that table 1 is analysed, is same as flow. (1)If Kp is high, PV is near fast to the SV, but Kp is small, PV is near slowly to the SV. (2)If Ki is shot, PV is close fast to the SV, but Ti is high, PV is close slowly to the SV (3)If Td is high, the variable rate of E press hardly when because it doesn\`t increase, but Td is small, the variable rate of E press not hardly, upper with 1), 2), PID module is supposed that be able to do the A/S and an implementation of that apparatus, and getting a success of aim that an engineer want, on control of temperature, tension, velocity, amount of flow, power of wind end so on, to get the principle of automatic implementation in industrial field with cooperation of A/D and D/A module.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.8
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• pp.3435-3454
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• 2016

Device-to-device (D2D) communication is a potential solution to the incessant increase in data traffic on cellular networks. The greatest problem is how to control the interference between D2D users and cellular mobile users, and between D2D users themselves. This paper proposes a solution for this issue by putting the full control privilege in cellular network using the software-defined networking (SDN) concept. A software virtual switch called Open vSwitch and several components are integrated into mobile devices for data forwarding and radio resource mapping, whereas the control functions are executed in the cellular network via a SDN controller. This allows the network to assign radio resources for D2D communication directly, thus reducing interference. This solution also brings out many benefits, including resource efficiency, energy saving, topology flexibility, etc. The advantages and disadvantages of this architecture are analyzed by both a mathematical method and a simple implementation. The result shows that implementation of this solution in the next generation of cellular networks is feasible.

• Journal of the Korean Society for information Management
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• v.19 no.2
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• pp.93-108
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• 2002

The purpose of this paper is to propose an successful implementation plan for national R&D program integrated information system. First, we surveyed and analyzed the status and plan of the national R&D program information system in developed countries (especially, the United States and Japan) Second, we reviewed the implementation background, limitation and further plan of the information systems related to R&D program in Korea. Last, division of the work and an successful plan in implementing the national R&D program integrated information system are discussed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.234-243
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• 1995

An arry circuit is designed for parallel computation of vector-radix 2-D discrete cosine transform (VR-FCT) which is a fast algorithm of DCT. By using a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently implemented with high condurrency and local communication geometry. The proposed implementation features architectural medularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. The array core for (8$\times$8) 2-D DCT, which is designed usign ISRC 1.5.mu.m N-Well CMOS technology, consists of 64 PEs arranged in (8$\times$8) 2-D array and contains about 98,000 transistors on an area of 138mm$^{2}$. From simulation results, it is estimated that (8$\times$8) 2-D DCT can be computed in about 0.88 .mu.sec at 50 MHz clock frequency, resulting in the throughput rate of about 72${\times}10^[6}$ pixels per second.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.239-242
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• 2003

Although most of all modern Web contents accomplished by passive interface which used 2D, by way of developing super-highway internet net and a 3D compression technology, it gradually changed VR Web3D. In this approach, we presents a recently VR tech. as well as the implementation of Web3D based on VR mapping tools.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.405-406
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• 2008

This paper presents a high performance 2D PE architecture for H.264 Motion Estimation(ME). While existing 2D PE architectures reuse the overlapped data of adjacent search windows scanned in 1 or 3-way, the new architecture scan adjacent windows and multiple paths instead of single raster and zigzag scanning of adjacent windows in 4 way(up,down,left,right). By reducing the redundant access factor by 1.4, the new 4-way search window improve the memory bandwidth by 70-58% compared with 1/3-way search window. With Altera Stratix-III implementation, the high performance 2D PE architecture deals with SD ($720{\times}480$) video of 2 reference frame, $48{\times}48$ search area and $16{\times}16$ macroblock by 30fps at 97.1MHz.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.371-372
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• 2007

In this paper we present performance and implementation comparisons of high performance two dimensional forward and inverse Discrete Cosine Transform (2D-DCT/IDCT) algorithm and low power algorithm for $8{\times}8$ 20 DCT and quantization based on partial sum and its corresponding hardware architecture for FPGA in MPEG-4. The architecture used in both low power 20 DCT and 2D IDCT is based on the conventional row-column decomposition method. The use of Fast algorithm and distributed arithmetic(DA) technique to implement the DCT/IDCT reduces the hardware complexity. The design was made using Mentor Graphics Tools for design entry and implementation. Mentor Graphics ModelSim SE6.1f was used for Verilog HDL entry, behavioral Simulation and Synthesis. The 2D DCT/IDCT consumes only 50% of the Operating Power.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1983.10a
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• pp.52-55
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• 1983