• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.11a
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• pp.200-202
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• 2014

본 논문은 High bit-depth 를 위한 SIMD (Single Instruction, Multiple Data) 명령어 기반 보간 필터 고속화 방법을 제안한다. 픽셀 연산을 기반으로 하는 보간 필터링은 HEVC 복호화기에서 높은 복잡도를 차지하고 있지만 반복적인 산술연산을 수행하기 때문에 SIMD 를 이용한 고속화에 적합한 구조를 가지고 있다. 이러한 이유로 본 논문에서는 보간 필터 연산에 대하여 SIMD 명령어를 이용하여 메모리를 효율적으로 사용하여 고속화하는 방법을 제안한다. 제안하는 기술은 HEVC 참조 소프트웨어 HM 12.0-RExt 4.1 에 기반을 둔 ANSI C 기반 자체 개발 HEVC RExt 복호화기 소프트웨어에서 평균 8.5%의 복호화 속도향상을 보였으며, 보간 필터의 수행 시간을 평균 24.8% 향상시켰다.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.05a
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• pp.126-128
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• 2023

본 논문에서는 2-bit RISC-V 프로세서 상에서의 경량 블록 암호인 SPECK의 CTR 운용 모드에 대한 최적 구현을 제안한다. RISC-V 상에서의 SPECK 단일 평문과 2개의 평문에 대한 최적화와 고정된 논스 값을 사용하는 CTR 운용모드의 특징을 활용하여 일부 값에 대해 사전 연산을 하는 라운드 함수 최적화를 제안한다. 결과적으로, 레퍼런스 대비 제안된 기법은 단일 평문과 2개의 평문에 대해 각각 5.76배 2.24배 성능 향상을 확인하였으며, 사전 연산 기법을 적용하지 않은 최적 구현 대비 사전 연산 기법을 적용하였을 때, 1% 성능 향상을 확인하였다.

• International Journal of Computer Science & Network Security
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• v.24 no.4
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• pp.206-210
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• 2024

Industrial facilities that use modern IT technologies require the ensured reliability and security of information in automated enterprise management. Concurrently, so as to ensure a high quality of communication, it is necessary to expand the bandwidth of communication channels, which are limited by the physical parameters of the radio frequency spectrum. In order to overcome this contradiction, we propose the application of technology fundamental to ultra-wideband signals, in which the ratio between the bandwidth and its central part is greater than "one". For this reason, the information signal is emitted without a carrier frequency - simultaneously within the entire frequency band - provided that the signal level is lower than the noise level. For the transmission of information content, the method of positional-time coding is used, in which each information bit is encoded by hundreds of ultrashort pulses that arrive within a certain sequence. Mathematical models of signals and values observed in wireless communication systems with autocorrelation reception of modulated ultra-wideband signals are furthermore recommended. These assist in identifying features of the dependence of the error probability on the normalized signal-to-noise ratio and the signal base. Comparative analysis has shown that the best noise immunity of the systems considered in this paper is the communication system, which uses the time separation of the reference and information signals. During the first half of the bit interval, the switch closes the output of the transmitter directly to the generator of the ultra-wideband signal - forming a reference signal. In the middle of the bit interval, the switch alternates the output to one of two possible positions depending on the encoding signal - "zero" or "one", forming the information part of the ultra-wideband signal. It should also be noted that systems with autocorrelation reception and separate transmission of reference and information signals, provide a high level of structural signal secrecy. Furthermore, they provide the reliable transmission of digital information, especially in interference conditions.

• ETRI Journal
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• v.33 no.5
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• pp.752-758
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• 2011

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.

• ETRI Journal
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• v.26 no.6
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• pp.583-588
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• 2004

In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of $3.63{\mu}m^2$. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when $V_{cc}$ is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1227-1237
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• 1999

In this paper, we present an oblivious transfer protocol which is the protocol for the fair exchange of secrets. For this, we investigate the verifiable oblivious transfer protocol based on discrete logarithm broblem proposed by Lein Ham etc. And we propose a new obivious transfer protocol that has the additional functions on the existing method. This proposed method has the additional functions that enable to authenticate sender and to protect denial of what he/she has sent message to the other. To do this, we make use of bit commitment scheme and digital signature scheme based on RSA.

• Progress in Superconductivity and Cryogenics
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• v.7 no.1
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• pp.21-24
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• 2005

The problem of fluctuation-induced digital errors in a rapid single flux quantum (RSFQ) circuit has been very important issue. So in this experiment, we calculated error rate of RSFQ switch in superconductiyity ALU, The RSFQ switch should have a very low error rate in the optimal bias. We prepared two circuits Placed in parallel. One was a 10 Josephson transmission lines (JTLs) connected in series, and the other was the same circuit but with an RSFQ switch placed in the middle of the 10 JTLs. We used a splitter to feed the same input signal to the both circuits. The outputs of the two circuits were compared with an RSFQ XOR to measure the error rate of the RSFQ switch. By using a computerized bit error rate test setup, we measured the bit error rate of 2.18$\times$$10^{12}$ when the bias to the RSFQ switch was 0.398mh that was quite off from the optimum bias of 0.6mA.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.7
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• pp.3455-3474
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• 2018

As a unique form of signed-digit representation, non-adjacent form (NAF) minimizes Hamming weight by removing a stream of non-zero bits from the binary representation of positive integer. Thanks to this strong point, NAF has been used in various applications such as cryptography, packet filtering and so on. In this paper, to improve the NAF conversion speed of the $NAF_w$ algorithm, we propose a new NAF conversion algorithm, called w-bit Shifting Non-Adjacent Form($SNAF_w$), where w is width of scanning window. By skipping some unnecessary bit comparisons, the proposed algorithm improves the NAF conversion speed of the $NAF_w$ algorithm. To verify the excellence of the $SNAF_w$ algorithm, the $NAF_w$ algorithm and the $SNAF_w$ algorithm are implemented in the 8-bit microprocessor ATmega128. By measuring CPU cycle counter for the NAF conversion under various input patterns, we show that the $SNAF_2$ algorithm not only increases the NAF conversion speed by 24% on average but also reduces deviation in the NAF conversion time for each input pattern by 36%, compared to the $NAF_2$ algorithm. In addition, we show that $SNAF_w$ algorithm is always faster than $NAF_w$ algorithm, regardless of the size of w.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.6 no.4
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• pp.3-38
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• 1996

The mobile station shall convolutionally encode the data transmitted on the reverse traffic channel and the access channel prior to interleaving. Code symbols output from the convolutional encoder are repeated before being interleaved except the 9600 bps data rate. All the symbols are then interleaved, 64-ary orthogonal modulation, direct-sequence spreading, quadrature spreading, baseband filtering and QPSK transmission. The sync, paging, and forward traffic channel except the pilot channel in the forward CDMA channel are convolutionally encoded, block interleaved, spread with Walsh function at a fixed chip rate of 1.2288 Mcps to provide orthogonal channelization among all code channels. Following the spreading operation, the I and Q impulses are applied to respective baseband filters. After that, these impulses shall be transmitted by QPSK. Authentication in the CDMA system is the process for confirming the identity of the mobile station by exchanging information between a mobile station and the base station. The authentication scheme is to generate a 18-bit hash code from the 152-bit message length appended with 24-bit or 40-bit padding. Several techniques are proposed for the authentication data computation in this paper. To protect sensitive subscriber information, it shall be required enciphering ceratin fields of selected traffic channel signaling messages. The message encryption can be accomplished in two ways, i.e., external encryption and internal encryption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.18-24
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• 2011

In multibit Sigma-Delta Modulator, one of the DEM(Dynamic Element Matching) techniques which is DWA(Data Weighted Averaging) is widely used to get rid of non-linearity caused by mismatching of capacitor that is unit element of feedback DAC. In this paper, by adjusting clock timing used in existing DWA architecture, 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. After designing the 3rd 3-bit SC(Switched Capacitor) Sigma-Delta Modulator by using the proposed DWA architecture, 0.1% of mismatching into unit element in input frequency 20 kHz and sampling frequency 2.56 MHz. As a consequence of the simulation, It was able to get the same resolution as the existing architecture and was able to reduce the number of MOS Tr. by 222.