• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.10
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• pp.826-831
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• 2009

In this paper, a high power RF amplifier module using AlN substrate of high thermal conductivity has been proposed. This RF amplifier module has the advantage of compact size and effective heat dissipation for the packaging of high power chip. To fabricate the thru-hole and scribing line on AlN substrate, the key parameters of $CO_2$ laser were experimented. And then, microstrip lines and spiral planar inductors were fabricated on an AlN substrate using the thin-film process. The fabricated microstrip lines on the AlN substrate has an attenuation value of 0.1 dB/mm up to 10 GHz. The fabricated spiral planar inductor has a high quality factor, a maximum of about 62 at 1 GHz for a 5.65 nH inductor. Packaging of a RF power amplifier was implemented on an AlN substrate with thru-hole. From the measured results, the gain is 24 dB from 13 to 15 GHz and the output power is 33.65 dBm(2.3 W).

• ETRI Journal
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• v.26 no.6
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• pp.589-596
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• 2004

Packaging technologies for a broadband and narrowband modulator with a traveling wave electro-absorption modulator (TWEAM) device were developed. In developing a broadband modulator, the effects of the device and packaging designs on the broadband performance were investigated. The optimized designs were obtained through a simulation with the result that we developed a broadband modulator with a 3 dB bandwidth of 38 GHz in the electrical-to-optical (E/O) response, an electrical return loss of less than -10 dB at up to 26 GHz, an rms jitter of 1.832 ps, and an extinction ratio of 5.38 dB in a 40 Gbps non-return to zero (NRZ) eye diagram. For analog application, the effect of the RF termination scheme on the fractional bandwidth was studied. The microstrip line with a double stub as a matching circuit and a laser trimming process were used to obtain an $S_{11}$ of -34.58 dB at 40 GHz and 2.9 GHz bandwidth of less than -15 dB.

• Electronics and Telecommunications Trends
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• v.32 no.6
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• pp.17-26
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• 2017

Electronic packaging technology is a technology that easily connects devices to the outside. The fourth industrial revolution is thought to be possible with the advancement of certain devices. The advancement of these devices must be accompanied by innovations in electronic packaging that connects the devices to the outside world, allowing their performances to be implemented at the system level. In this paper, the development trends of 2.5D/3D technology, heterogeneous integration technology, ultrafine interconnection technology, and heat dissipation technology will be examined, and the development direction of these technologies will be discussed.

• Journal of Korea Technical Association of The Pulp and Paper Industry
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• v.29 no.3
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• pp.69-81
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• 1997

Up to now 5 Voith Sulzer paper machines with multi-layer headbox and Gapfor-mer are sucessfully running on papckaging papers. Linerboard, testliner and corugating medium is produced in the basis weight range from 105 to 275 $g/m^2$ at machine speeds up to 900 m/min. The nest one, starting up in Oct. ｀96 in Germany, will be the world＇s fastest paper machine for packaging papers. The 5.6 m wide machine is designed for a maximum operating speed of 1200 m/min. Approx. 220.000 tons of corrugating medium and testliner based on 100% waste paper in the basis weight range from 90 to 160 $g/m^2$ will be produced each year. An expansion stage planned for the future is intended to increase annual output to 280.000 tons. This machine will not only be the fastest one for packaging papers, it also comprises all described innovative key components which are available today in order to fulfill growing demands of the future with regard to quality and productivity. The concept of this advanced machine is shown in Fig. 9.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.3
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• pp.1-7
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• 2021

In this paper, by embedding a bare-die chip-type drive amplifier into the PCB composed of ABF and FR-4, it implements an embedded active device that can be applied in 28 GHz band modules. The ABF has a dielectric constant of 3.2 and a dielectric loss of 0.016. The FR-4 where the drive amplifier is embedded has a dielectric constant of 3.5 and a dielectric loss of 0.02. The proposed embedded module is processed into two structures, and S-parameter properties are confirmed with measurements. The two process structures are an embedding structure of face-up and an embedding structure of face-down. The fabricated module is measured on a designed test board using Taconic's TLY-5A(dielectric constant : 2.17, dielectric loss : 0.0002). The PCB which embedded into the face-down expected better gain performance due to shorter interconnection-line from the RF pad of the Bear-die chip to the pattern of formed layer. But it is verified that the ground at the bottom of the bear-die chip is grounded Through via, resulting in an oscillation. On the other hand, the face-up structure has a stable gain characteristic of more than 10 dB from 25 GHz to 30 GHz, with a gain of 12.32 dB at the center frequency of 28 GHz. The output characteristics of module embedded into the face-up structure are measured using signal generator and spectrum analyzer. When the input power (P_in) of the signal generator was applied from -10 dBm to 20 dBm, the gain compression point (P_1dB) of the embedded module was 20.38 dB. Ultimately, the bare-die chip used in this paper was verified through measurement that the oscillation is improved according to the grounding methods when embedding in a PCB. Thus, the module embedded into the face-up structure will be able to be properly used for communication modules in millimeter wave bands.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.11a
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• pp.61-64
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• 2000

We fabricated and characterized Low Noise Amplifier (LNA) using MCM-C (Multi-Chip-Module-Cofired) technology for 2.14 GHz IMT-2000 mobile terminal application. First, We designed LNA circuits and simulated it's high frequency characteristics using circuits simulator. For the simulation, we adopted high frequency libraries of all the devices used in LNA samples. By the simulation, Gain was 17 dB and Noise Figure was 1.4 dB. We used multilayer process of LTCC (Low Temperature Co-fired Ceramics) substrate and conductor, resistor pattern for the MCM-C LNA fabrication. We made 2 buried inductors, 2 buried capacitors and 3 buried resistors. The number of the total layers was 6. On the top layer, we patterned microstrip line and pads for the SMT device. We measured the high frequency characteristics, and the results were 14.7 dB Gain and 1.5 dB Noise Figure.

• Journal of the Microelectronics and Packaging Society
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• v.5 no.2
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• pp.13-20
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• 1998

고속 디지털 MCM 응용을 위해 MCM-D 와 MCM-SLC 배선에서 CMOS 버퍼의 신호상승시간에 따른 신호전송특성을 연구하였다. 고속신호처럼 버퍼의 내부저항이 배선의 임피던스보다 작아 발생하게 되는 과도한 ringing은 MCM-D와 같이 lossy line의 전송감쇠 효과로 overshooting 이나 undershooting을 줄일 수 있지만 ringing에 의한 신호왜곡을 근 본적으로 막기위해서는 CMOS버퍼와 배선사이에 적절한 종단을 통해 임피던스 비해 크면 배선의 캐패시턴스에 의해 RC 지연이 증가한다. 그런데 MCM-D 배선은 단위길이당 캐패 시턴스도 작고 배선길이를 줄일수 있으므로 총 RC 지연은 MCM-SLC보다 작았다. 결론적 으로 MCM-D 배선이 MCM-SLC 배선에 비해 고속 디지털 MCM기판으로 적합한 것을 알 수 있었다.

• Korean Journal of Food Science and Technology
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• v.28 no.6
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• pp.1177-1179
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• 1996

A static headspace gas chromatographic (HSGC) technique was used to quantify toluene and other solvents (methanol, isopropyl alcohol, methyl ethyl ketone and ethyl acetate) in food packaging films. Comparison of retention times and coefficient variations for standard solvents showed consistent retention time and good reproducibility. Therefore, this method using static HSGC proved to be superior in rapidity and reproducibility, and is thought to be adaptable to analysis of a large number of samples. The methanol content was $N.D.\;(not\;detected){\sim}0.939\;mg/m^2$, toluene $N.D.{\sim}1.403\;mg/m^2$, melthyl ethyl ketone $N.D.{\sim}0.932\;mg/m^2$, total solvent content was $N.D.{\sim}2.433\;mg/m^2$.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1502-1503
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• 2007

In this paper, inductive coupled LC balun has been desi gned and simulated for embedding into an organic packaging substrate. Inductive coupling method was applied to obtain wide band characteristics, and high dielectric film was utilized to reduce a size of the balun. The proposed balun has a novel scheme which consists of three embedded LC resonators with inductive coupling. This proposed balun has relatively small inductance and capacitance values which can be easily embedded into the organic packaging substrate. Furthermore, it has a good phase imbalance characteristic. The simulated results of proposed balun are an insertion loss of 1.2 dB, a return loss of 10 dB, a phase imbalance of 1 degree at frequency bandwidth of 750 MHz ranged from 1.8 GHz to 2.55 GHz, respectively. This balun has an area of $2mm{\tims}3.5mm{\times}0.66mm$ (height).

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)