• Journal of the Korean Magnetic Resonance Society
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• v.5 no.1
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• pp.29-36
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• 2001

The structures of two VBS (viral binding site) RNAs, SL1 and SL2, of Yeast Saccharomyces cerevisiae vims have been studied by 2D and 3D NMR experiments. VBSs play a crucial role in viral particle binding to the plus strand and packaging of the RNA. The secondary structures of the two VBS RNAs share a common feature of the stem-internal loop-stem-hairpin loop structure although the size of the internal loops of SL1 and SL2 differs. 2D experiments were sufficient for fill assignments of SL1. However, isotope labeling of the sample and multidimensional experiments were required for 28-nucleotide-long SL2 due to the spectral overlap. Several 3D HCCH experiments have accomplished full assignment of SL2 RNA.

• Journal of Korea Technical Association of The Pulp and Paper Industry
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• v.35 no.2
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• pp.33-38
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• 2003

In order to design the high strength corrugated fiberboard containers for agricultural products that can be used for the cold chain system, a large number of individual boxes were placed in various humidity environments at two different temperature of 5 and $20^{\circ}C$. The results indicated that temperature changes do not effect on physical strength of corrugated fiberboard containers as much as humidity changes did. The main conclusion from this study was that compression strength of corrugated fiberboard containers dropped significantly at high humidity condition, but the rates varied depending on the number of walls, temperature, and perimeter of containers. The packaging designer must consider the corrugated fiberboard boxes are also greatly affected by dimensional variations such as the length versus width ratio. Based on this study, water-resistant board would not be necessary if the ambient relative humidity does not reach to a critical point, 85 percent in the cold chain system. However, the designer must count for the unexpected fluctuation of rotative humidity resulting in severe loss of the compression strength of corrugated fiberboard container.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.1718-1723
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• 2007

The Probe Card is a test component which is to classify the good semiconductor chips before the packaging. The yield of semiconductor product can be better from analysis of probe test information. Recently the technology of the probe card needs narrow width and large amount of probe tip. In this research, the probe tip based on the MEMS(micro electro mechanical system) technology was designed and fabricated to improve the reliability of the test and to meet 2-dimensional Array of tip. The mechanical and electrical properties of proposed tip were evaluated and it has over 100,000 of repetition times in the condition of 5gf, $20{\mu}m$ Over Drive.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.49-53
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• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.77-86
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• 2008

The reliability of leaded and lead-free solders of BGA type packages on a printed circuit board was investigated by employing the standard drop test and 4-point bending test. Tested solder joints were examined by optical microscopy to identify associated failure mode. Three-dimensional finite element analysis(FEM) with ANSYS Workbench v.11 was carried out to understand the mechanical behavior of solder joints under the influence of bending or drop impact. The results of numerical analysis are in good agreement with those obtained by experiments. Packages in the center of the PCB experienced higher stress than those in the perimeter of the PCB. The solder joints located in the outermost comer of the package suffered from higher stress than those located in center region. In both drop and bending impact tests, the lead-free solder showed better performances than the leaded solders. The numerical analysis results indicated that stress and strain behavior of solder joint were dependent on various effective parameters.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.3
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• pp.45-54
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• 2000

The effect of electropolishing far stamped leadframe on the removal of the edge burr and residual stress relief was examined. The present study showed that the electropolishing could be used for enhanced surface quality of stamped leadframes. The electropolishing was performed at the condition of 60% phosphoric acid electrolyte, 5 ampere of current and 3 cm electrode gap at $70^{\circ}C$ for 2 minutes for Alloy42 type leadframe, and $50^{\circ}C$ for 1.5 minutes for C-194 type leadframe. The FWHM values from X-ray diffraction showed that residual stress of electropolished leadframe recovered to the level of as-received raw materials and surface roughness measured by using AFM tuned out to be improved by 0.079 $\mu\textrm{m}$ and 0.014 $\mu\textrm{m}$ ($R_{rms}$) far alloy 42 and C-194 type leadframes, respectively. The plated thickness using XRF showed the improved uniformity in thickness variation by 0.4~0.5 $\mu\textrm{m}$ and grain growth, which is favorable for interface adhesion, was also observed from the bake test samples. We could certify dimensional stability of leadframe with inspection by means of 3D-topography and hardness measurements.

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.