• Title/Summary/Keyword: 2-루프 구조

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Design of RF Energy Detector for Spectrum Sensing in TV White Space Transceiver (TV White Space 송수신기의 스펙트럼 센싱을 위한 RF 에너지 검출 회로 설계)

  • Kim, Jong-Sik;Shin, Hyun-Chol
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.11 no.2
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    • pp.83-91
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    • 2012
  • An RF energy detector for spectrum sensing in TV white space transceiver is presented. It is based on an RF active filtering technique that comprises a low-noise amplifier with a frequency-translation high-pass filtering feedfoward loop, which attenuates the unwanted sideband energy and only passes the wanted band energy. Unlike the conventional architecture, a new architecture that can attenuate both sidebands at the same time is proposed. A simplified system modeling method is presented to assess the non-ideality effects on the RF energy detector performances. System behavioral simulations demonstrate that the proposed architecture can be instrumental for realizaing a RF energy detector circuit in CMOS.

A 12b 1kS/s 65uA 0.35um CMOS Algorithmic ADC for Sensor Interface in Ubiquitous Environments (유비쿼터스 환경에서의 센서 인터페이스를 위한 12비트 1kS/s 65uA 0.35um CMOS 알고리즈믹 A/D 변환기)

  • Lee, Myung-Hwan;Kim, Yong-Woo;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.3
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    • pp.69-76
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    • 2008
  • This work proposes a 12b 1kS/s 65uA 0.35um CMOS algorithmic ADC for sensor interface applications such as accelerometers and gyro sensors requiring high resolution, ultra-low power, and small size simultaneously. The proposed ADC is based on an algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. Two versions of ADCs are fabricated with a conventional open-loop sampling scheme and a closed-loop sampling scheme to investigate the effects of offset and 1/f noise during dynamic operation. Switched bias power-reduction techniques and bias circuit sharing reduce the power consumption of amplifiers in the SHA and MDAC. The current and voltage references are implemented on chip with optional of-chip voltage references for low-power SoC applications. The prototype ADC in a 0.35um 2P4M CMOS technology demonstrates a measured DNL and INL within 0.78LSB and 2.24LSB, and shows a maximum SNDR and SFDR of 60dB and 70dB in versionl, and 63dB and 75dB in version2 at 1kS/s. The versionl and version2 ADCs with an active die area of $0.78mm^2$ and $0.81mm^2$ consume 0.163mW and 0.176mW at 1kS/s and 2.5V, respectively.

A Design of Ultra Wide-Band Feedforward Amplifier Using Equal Group-Delayed Signal Canceller (동일 군속도 지연 신호 상쇄기를 이용한 광대역 Feedforward증폭기 설계)

  • Jeong Yong-Chae;Ahn Dal;Kim Hong-Gi;Kim Chul-Dong;Chang Ik-Soo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.8 s.99
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    • pp.825-834
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    • 2005
  • In this paper, a new signal canceller that input signals are equally group-delayed and cancelled each other is proposed and feedforward linearizing power amplifier that adopt the proposed signal cancellers is fabricated. Although the conventional signal canceller can't matches the phase and the group delay time of input signals simultaneously, the proposed signal canceller matches those simultaneously. Simultaneous matching of the phase and the group delay time can makes wideband signal cancellation. The main signal cancellation loop of the fabricated feedforward amplifier with the proposed signal cancellers cancel input signal more than 26.3 dB and the intermodulation distortion signal cancellation loop cancel more than 15.2 dB for 200 MHz bandwidth. And the proposed feedforward power amplifier improves C/I ratio by 20.8 dB with two tones at 2,115 MHz, 2,165 MHz, respectively.

Implementation of an AAL2 processor for voice gateway application (음성 게이트웨이 응용을 위한 AAL2 프로세서 구현)

  • 이상길;최명렬
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.11C
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    • pp.1152-1157
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    • 2002
  • In this paper, a detailed procedure of development for an AAL2 processor widely used in voice gateway application is introduced. The processor supports CPS and SSCS with voice service and framed mode data service. It provides 4 ATM virtual connections, which include 1020 AAL2 channels. The processor has one UTOPIA Level 1 interface for an ATM cell interface and 4 TDM ports for a voice channel interface. The TDM ports carry PCM/ADPCM voice streams. Most AAL2 processors are implemented as software, or hardware and software, so its latency is large. But this processor has very low latency as to CPS and SSCS because all of them are implemented in hardware. Also, it allows not only loopback and switching of CPS packets, but loopback and switching of TDM channels. The key feature is that the internal structure of the CPS and SSCS in this processor seems like as each software function, so they are called whenever they are required. In addition, they are reusable for another design and are scalable for more channels.

Reduction Design on the Magnetic Noise by Pyro Initiator Activation of Space Launch Vehicle (우주발사체에 적용되는 파이로 기폭에 의한 자계노이즈 저감설계)

  • Hong, Il-Hee;Kim, Yang-Mo
    • Proceedings of the KIEE Conference
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    • 2006.10c
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    • pp.407-409
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    • 2006
  • 우주발사체I 상단 시스템은 비행 중에 킥 모터 점화, 위성분리와 같은 HBW 점화기 기폭이 순차적으로 발생 한다. HBW 점화기의 기폭시에는 일반적으로 전도성 구조물을 통한 단락전류가 일시적으로 발생한다. 이러한 단락전류는 구동 전원 측으로 최대 전류 값 및 루프 면적에 비례한 일시적인 자기장을 형성시키고 near 필드(${\lambda}/2{\pi}$) 내의 인접하게 위치한 하니스에 자계 결합을 통한 역기전력 발생의 원인이 될 수 있다. 이러한 인접 하니스에 자계 노이즈 결합은 여러 자료를 통해 우주시스템 환경에서 일시적인 데이터 손실의 원인이 되는 것으로 분석되고 있다. 본 논문은 우주발사체의 HBW 점화기 기폭시 발생되는 전도성 구조물 단락전류 귀환현상으로 인한 자계노이즈 분석 및 감쇄방안에 대해 논의하고자 한다.

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Design of a CMOS PLL with a Current Pumping Algorithm for Clock Syncronization (전류펌핑 알고리즘을 이용한 클락 동기용 CMOS PLL 설계)

  • 성혁준;윤광섭;강진구
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.1B
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    • pp.183-192
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    • 2000
  • In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

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A Study on the Weight-Reduction Design of High-Speed Maglev Carbody made of Aluminum Extrusion and Sandwich Composite Roof (알루미늄 압출재와 샌드위치 복합재 루프를 적용한 초고속 자기부상 열차의 차체 경량화 설계 연구)

  • Kang, SeungGu;Shin, KwangBok;Park, KeeJun;Lee, EunKyu;Yoon, IllRo
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.38 no.10
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    • pp.1093-1100
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    • 2014
  • The purpose of this paper is to suggest a weight-reduction design method for the hybrid carbody of a high-speed maglev train that uses aluminum extrusion profiles and sandwich composites. A sandwich composite was used on the roof as a secondary member to minimize the weight. In order to assemble the sandwich composite roof and aluminum extrusion side frame of the carbody using welding, a guide aluminum frame located at the four sides of the sandwich composite roof was introduced in this study. The clamping force of this guide aluminum frame was verified by three-point bending test. The structural integrity and crashworthiness of the hybrid carbody of a high-speed maglev train were evaluated and verified according to the Korean Railway Safety Law using a commercial finite element analysis program. The results showed that the hybrid carbody composed of aluminum extrusion frames and a sandwich composite roof was lighter in weight than a carbody made only of aluminum extrusion profiles and had better structural performance.

Improvement of a 4-Channel Spiral-Loop RF Coil Array for TMJ MR Imaging at 7T (7T 악관절 MRI를 위한 4 채널 스파이럴 RF 코일의 성능개선)

  • Kim, Kyoung-Nam;Kim, Young-Bo;Cho, Zang-Hee
    • Investigative Magnetic Resonance Imaging
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    • v.16 no.2
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    • pp.103-114
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    • 2012
  • Purpose : In an attempt to further improve the radiofrequency (RF) magnetic ($B_1$) field strength in temporomandibular joint (TMJ) imaging, a 4-channel spiral-loop coil array with RF circuitry was designed and compared with a 4-channel single-loop coil array in terms of $B_1$ field, RF transmit (${B_1}^+$), signal-to-noise ratio (SNR), and applicability to TMJ imaging in 7T MRI. Materials and Methods: The single- and 4-channel spiral-loop coil arrays were constructed based on the electromagnetic (EM) simulation for the investigation of $B_1$ field. To evaluate the computer simulation results, the $B_1$ field and ${B_1}^+$ maps were measured in 7T. Results: In the EM simulation result and MRI study at 7T, the 4-channel spiral-loop coil array found a superior $B_1$ performance and a higher ${B_1}^+$ profile inside the human head as well as a slightly better SNR than the 4-channel single-loop coil array. Conclusion: Although $B_1$ fields are produced under the influence of the dielectric properties of the subject rather than the coil configuration alone at 7T, each RF coil exhibited not only special but also specific characteristics that could make it suited for specific application such as TMJ imaging.

3-D Beam Steering Antenna for Intelligent Beam-reconfigurable System (지능형 빔 재구성 시스템을 위한 3-D 빔 조향 안테나)

  • Lee, Chang Yong;Kim, Yong-Jin;Jung, Chang Won
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.10
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    • pp.4773-4779
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    • 2012
  • In this paper we propose two types of reconfigurable 3-D beam steering antenna for intelligent or smart antenna system. Proposed antennas are composed of triangular(structure1.) or circuler(structure2.) loop structure and bended dipole antenna structure. This antenna can steer beam pattern of 6 direction at xy-plane state (0, 1, 2) and xz-plane state (3, 4, 5) by 4 switch motion with one antenna element. Antenna structure1. is symmetric equilibrium structures based on feeding point. There is no grounding point. As a result, designed antenna's gain is similar to dipole antenna. Also, As unbalanced structure by using CPWG in the form of a semicircular, structure2. is enhanced directivity. The operation frequency of antenna are 2.5 GHz(Structure1.) and 2.55 GHz(Structure2.), maximum gain is 1.04 ~ 2.06 dBi(Structure1. : Omni-directional beam), 1.6 ~ 4 dBi(structure2. : Directional beam). The overall HPBW is about over $160^{\circ}$ in the both of the xy-plane and xz-plane at structure1. and over $125^{\circ}$ at structure2.

Design of a 99dB DR single-bit 4th-order High Performance Delta-Sigma Modulator (99dB의 DR를 갖는 단일-비트 4차 고성능 델타-시그마 모듈레이터 설계)

  • Choi, Young-Kil;Roh, Hyung-Dong;Byun, San-Ho;Nam, Hyun-Seok;Roh, Jeong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.2
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    • pp.25-33
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    • 2007
  • In this paper, a fourth-order single-bit delta-sigma modulator is presented and implemented. The loop-filter is composed of both feedback and feedforward paths. Measurement results show that maximum 99dB dynamic range is achievable at a clock rate of 3.2MHz for 20kHz baseband. The proposed modulator has been fabricated in a $0.18{\mu}m$ standard CMOS process.