• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.18 no.1 s.116
• /
• pp.37-43
• /
• 2007

In this.paper, we introduce design and implementation results of the single balanced diode mixer for European point-to-point microwave radio in order to improve flatness performance. When a resonator such as RF filter is integrated with a mixer, impedance characteristic of 50 ohm is maintained only in RF band, not in LO band resulting deterioration of flatness performance because of LO power variation on the diode. In the paper, we suggest a design method of mixer integrated with image rejection filter and LO harmonic filter to have a better performance of flatness using embedding electrical length between filter and mixer's port. Frequency specification of fabricated mixer is $21.2{\sim}22.6\;GHz$ for RF, $19.32{\sim}20.72\;GHz$ for LO and 1.88 GHz+/-50 MHz for IF, respectively. Measured results show conversion loss of 8.5 dB, flatness of 2 dB, input PldB of 8 dBm, IIP3 of 15 dBm under LO power level of 10 dBm. Return losses of RF, LO and IF port are under -12 dB, -10 dB and -5 dB, respectively. Isolations of LO/RF and LO/IF are 20 dB and 50 dB, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.11 no.1
• /
• pp.84-92
• /
• 2000

A GaAs MESFET MMIC transmitter for 2.4 GHz wireless local loop handset is designed and fabricated. The transmitter consists of a double balanced active mixer and a two stage driver amplifier with voltage negative feedback. In particular, a pair of CS-CG(common source-common gate) structure compensates the reduction in dynamic range caused by unbalanced complementary IF input signals. And to suppress the leakage local power at RF port, the mixer is designed by using phase characteristic between the ports of MESFET. At the bias condition of 2.7 V and 55.2 mA, the fabricated MMIC transmitter with chip dimensions of $0.75\times1.75 mm^2$ obtains a measured conversion gain of 38.6 dB, output $P_{idB}$ of 11.6 dBm, and IMD3 at -5 dBm RF output power of -31.3 dBc. This transmitter is well suited for WLL handset.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.12
• /
• pp.91-96
• /
• 2011

In this paper, a low-power direct-conversion transmitter based on current-mode operation, which satisfies the IEEE 802.15.4 standard, is proposed and implemented in a $0.13{\mu}m$ CMOS technology. The proposed transmitter consists of DACs, LPFs, variable gain I/Q up-conversion mixer, a divide-by-two circuit with LO buffer, and a drive amplifier. By combining DAC, LPF, and variable gain I/Q up-conversion mixer with a simple current mirror configuration, the transmitter's power consumption is reduced and its linearity is improved. The drive amplifier is a cascode amplifier with gain controls and the 2.4GHz I/Q differential LO signals are generated by a divide-by-two current-mode-logic (CML) circuit with an external 4.8GHz input signal. The implemented transmitter has 30dB of gain control range, 0dBm of maximum transmit output power, 33dBc of local oscillator leakage, and 40dBc of the transmit third harmonic component. The transmitter dissipates 10.2mW from a 1.2V supply and the die area of the transmitter is $1.76mm{\times}1.26mm$.

• Tribology and Lubricants
• /
• v.26 no.1
• /
• pp.44-51
• /
• 2010

A miniature shear testing machine was designed and developed, adopting a piezoelectric actuator with mechanical advantage using 4 levers in order to investigate shear behavior of a small solder ball. The final output displacement was initially expected to be 2.88 mm without load resistance, considering the lever ratio of 24 and the piezo displacement of 0.12 mm with an exciting voltage of 10 V. However, the final plunger displacement ${\Delta}{\upsilon}$ can be expected as ${\Delta}{\upsilon}=2.88-3.04{\times}10^{-4}F$ as a function of piezoelectric force F due to the stiffness of various levers and connectors and piezo actuator. The shear behavior of lead-free solder ball in diameter of $760{\mu}m$ was successfully investigated in a speed range of 2 mm/s~0.0035 mm/s using this designed device.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.1
• /
• pp.8-16
• /
• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Journal of ILASS-Korea
• /
• v.28 no.2
• /
• pp.62-67
• /
• 2023

Recently, the global automobile industry is aiming for a transition from internal combustion locomotives to zero-emission vehicles. Electric vehicles powered by battery energy can operate at peak performance and improve fuel economy by applying multiple motors or multi-speed transmissions. In order to design a two-speed transmission, it is necessary to evaluate and analyze the application system and performance of electric vehicles. In this study, control performance optimization of a twostage battery electric vehicle equipped with an AMT-based automatic transmission was performed and performance according to control pattern changes was analyzed. In order to improve the operating efficiency of the motor, the shift control that sets the optimal operating point according to the vehicle speed and required torque was derived from the motor efficiency map. The performance of battery energy consumption and transmission loss energy according to the hysteresis interval was analyzed and optimized. The hysteresis interval applied to the optimal shift map acted as a factor in reducing the frequency and loss of shifts. It has been shown that keeping the hysteresis interval at about 4 km/h can reduce energy consumption while reducing the number of shifts.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 2000.06a
• /
• pp.1533-1539
• /
• 2000

In this paper, we propose a design method using Taguchi method and a neural network. Using this method, we can design a dual-stage actuator having the required tracking/focusing properties in real time. Also, as an application of this method, a proposed dual-stage pick-up actuator having the required properties was designed. The seek time of this designed actuator is less than 13 msec by a time optimal technique. Simulation results show that this method can potentially be implemented in all the dual-stage actuators.

• Proceedings of the KIPE Conference
• /
• 2010.07a
• /
• pp.214-215
• /
• 2010

본 논문은 공진 인버터를 적용한 HID램프를 구동하기 위한 전자식 안정기를 설계하고 구현하였다. 제안된 전자식 안정기는 스위치 턴온 오프시의 손실을 줄이기 위해서 소프트 스위칭 기법인 ZVS(Zero-Voltage Switching)을 도입하였다. 점등은 LC필터의 공진주파수범위에서 풀브리지 인버터 제어에 의한 공진으로 이루어 진다. 점등후에 컨버터는 저주파수 구형파로 동작한다. 공진 기동시의 LC필터의 공진주파수는 ($f_o$=160kHz)이고, 고조파를 감소시키고 음향공진현상을 피하기 위한 벅컨버터 스위칭 주파수(고주파수 : 50~60kHz 와 저주파수 : 170Hz)를 선택하였다. 실험을 통해 공진 인버터를 적용한 HID램프용 전자식 안정기가 안정적으로 동작함을 확인하였다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.12
• /
• pp.3235-3245
• /
• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• The Bulletin of The Korean Astronomical Society
• /
• v.37 no.2
• /
• pp.151.2-151.2
• /
• 2012

터보펌프 구동에 사용된 가스발생기 생성가스를 연소기로 공급하여 주추력 발생에 사용하는 다단연소 사이클 로켓엔진은 고추력을 요하는 우주 발사체에 널리 사용되고 있다. 다단연소 사이클 로켓엔진에 사용되는 가스발생기를 예연소기라 부르며 케로신과 액체산소를 추진제로 하는 다단연소 사이클 로켓엔진에는 산화제 과잉 예연소기가 사용된다. 예연소기는 터보펌프 구동을 목적으로 하기 때문에 예연소기 생성가스의 횡단면 온도분포는 터빈에 의해 제한되는 온도범위 내에서 균일하여야 하며 넓은 운전영역에서 안정적인 연소가 이루어져야 한다. 산화제 과잉 예연소기는 모든 추진제가 혼합헤드를 통해 분사되는 방식과 추진제를 혼합헤드와 연소실로 나누어 공급하는 방식이 있다. 기술검증을 위해 산화제 일부와 연료를 혼합헤드를 통해 연소실에 공급하여 1차 연소시키고 나머지 산화제를 연소실 냉각채널을 거쳐 연소실 중앙의 분사공을 통해 연소실로 주입하여 기화시키는 형태로 최종적으로 연소압 20MPa, 혼합비 60에서 작동하는 산화제 과잉 예연소기를 설계하여 연소시험을 수행하였다. 혼합헤드에는 별도의 점화용 분사기 없이 전체 연료 분사기를 통해 점화용 연료인 TEA/TEB 혼합물을 분사하여 점화하였다. 추진제를 2단으로 공급할 수 있도록 고안된 가압식 연소시험 설비에서 10회, 누적 60초 이상의 연소시험이 성공적으로 수행되었다. 연소시험결과 넓은 작동영역에서 안정적 연소특성과 생성가스 온도 분포의 균일성을 확인할 수 있었다. 고온 고압의 산화제 과잉 예연소기 기술 확보를 통해 케로신/액체산소 다단연소 사이클 로켓엔진 개발을 위한 기술적 기반을 마련하였다.