• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.151-153
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• 2006

When distributed powers are interconnected to the grid, lack of source stability may cause some events that should be measured and stored as soon as they occur. This paper presents a real-time hardware system that has been developed for quick and reliable monitoring of the distributed powers quality. The system is composed of a digital signal processor (MPC7410, Motorola) and a 16 bits A/D board (VMIVME3122, GE). To guarantee the real time operation, it is based on a real time OS (VxWorks). Hardware tests of the embedded system have been made to check the performances of the proposed system. Test signals of several events are generated by using a LabView (hardware) system. The tests show that the system complies with the desired IEEE standard for power quality monitoring.

• The Journal of the Acoustical Society of Korea
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• v.20 no.7
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• pp.63-68
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• 2001

This paper describes the details of ITU-T SGIS G.729A speech coder implementation using ARM9 Thumb/sup R/ processor core and various techniques used in the optimization process. ITU-T G.729 speech coder is the standard of the toll quality 8 kbit/s speech coding. The input to the speech encoder is assumed to be a 16 bits PCM signal at a sampling rate of 8000 samples per second. G.729A is reduced complexity version of the G.729 coder. This version is bit stream interoperable with the full version. The implemented coder requires 34.8 MIPS for the encoder and 8.1 MIPS for the decoder, 36.5 kBytes of program ROM and 6.3 kBytes of data RAM, respectively. The implemented coder is tested against the set of 9 test vectors provided by ITU-T for bit exact implementation.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.252-259
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• 2007

With the rapid development of multimedia applications and wireless communication networks, consumer demand for video-over-wireless capability on mobile computing systems is growing rapidly. In this regard, this paper introduces YUV-aware instructions that enhance the performance and efficiency in the processing of color image and video. Traditional multimedia extensions (e.g., MMX, SSE, VIS, and AltiVec) depend solely on generic subword parallelism whereas the proposed YUV-aware instructions support parallel operations on two-packed 16-bit YUV (6-bit Y, 5-bits U, V) values in a 32-bit datapath architecture, providing greater concurrency and efficiency for color image and video processing. Moreover, the ability to reduce data format size reduces system cost. Experiment results on a representative dynamically scheduled embedded superscalar processor show that YUV-aware instructions achieve an average speedup of 3.9x over the baseline superscalar performance. This is in contrast to MMX (a representative Intel#s multimedia extension), which achieves a speedup of only 2.1x over the same baseline superscalar processor. In addition, YUV-aware instructions outperform MMX instructions in energy reduction (75.8% reduction with YUV-aware instructions, but only 54.8% reduction with MMX instructions over the baseline).

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.123-133
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• 2017

In this paper, we developed an optimal flicker-free control algorithm operating within 16 luminance implementation bits and 512 brightness implementation pulses irrespective of LPM(LED Pixel Matrix) module configuration on dynamic driving method of LED display system. As an implementation method, we turned the refresh rate up by increasing the number of scans through multiple shift-latches which were devised from conventional shift-latch scheme for full color representation. As a result, the LED display system of this method has no flicker phenomenon because of the novel refresh rate higher than 2,040[Hz] incomparable to 240~480[Hz] of conventional system.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.7
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• pp.305-317
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• 2008

As a mobile computing environment is rapidly changing, increasing user demand for multimedia-over-wireless capabilities on embedded processors places constraints on performance, power, and sire. In this regard, this paper proposes color media instructions (CMI) for single instruction, multiple data (SIMD) parallel processors to meet the computational requirements and cost goals. While existing multimedia extensions store and process 48-bit pixels in a 32-bit register, CMI, which considers that color components are perceptually less significant, supports parallel operations on two-packed compressed 16-bit YCbCr (6 bit Y and 5 bits Cb, Cr) data in a 32-bit datapath processor. This provides greater concurrency and efficiency for YCbCr data processing. Moreover, the ability to reduce data format size reduces system cost. The reduction in data bandwidth also simplifies system design. Experimental results on a representative SIMD parallel processor architecture show that CMI achieves an average speedup of 6.3x over the baseline SIMD parallel processor performance. This is in contrast to MMX (a representative Intel's multimedia extensions), which achieves an average speedup of only 3.7x over the same baseline SIMD architecture. CMI also outperforms MMX in both area efficiency (a 52% increase versus a 13% increase) and energy efficiency (a 50% increase versus an 11% increase). CMI improves the performance and efficiency with a mere 3% increase in the system area and a 5% increase in the system power, while MMX requires a 14% increase in the system area and a 16% increase in the system power.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.284-287
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• 1987

In this paper, the design and implementation of a multiprocessor based Die Bonder Machine for the semiconductor will be described. This the partial research result, that is, the 1st year portion of the project to be performed for a period of two years from June, 1986 to May, 1988. The mechanical system consists of the following three subsystems : (i) transfer head unit, (ii) die feeding XY-table unit, and (iii) plunge up unit. The overall control system is designed to be essentially a master-slave type in which each slave is functionally fixed in view of software and also the time shared common bus structure with hardwired bus arbitration scheme is utilized, the control system consists of the following three subsystems each of which employs a 16 bits microprocessor MC 68000 : (i) die bonder processor controller, (ii) visual recognition/inspection and display system, (iii) the servo control system. It is reported that the proposed control system were applied to Working Sample and tested in real system, and the results are successful as a working sample phase.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8C
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• pp.575-582
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• 2008

In this paper we described the process and the results of real-time implementation of G.729.1 wideband speech codec which is standardized in SG15 of ITU-T. To apply the codec on ARM926EJ-S(R) processor core. we transformed some parts of the codec C program including basic operations and arithmetic functions into assembly language to operate the codec in real-time. G.729.1 is the standard wideband speech codec of ITU-T having variable bit rates of $8{\sim}32kbps$ and inputs quantized 16 bits PCM signal per sample at the rate of 8kHz or 16kHz sampling. This codec is interoperable with the G.729 and G.729A and the bandwidth extended wideband($50{\sim}7,000Hz$) version of existing narrowband($300{\sim}3,400Hz$) codec to enhance voice quality. The implemented G.729.1 wideband speech codec has the complexity of 31.2 MCPS for encoder and 22.8 MCPS for decoder and the execution time of the codec takes 11.5ms total on the target with 6.75ms and 4.76ms respectively. Also this codec was tested bit by bit exactly against all set of test vectors provided by ITU-T and passed all the test vectors. Besides the codec operated well on the Internet phone in real-time.