• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1675-1685
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• 2012

DVC (Distributed Video Coding) technique plays an essential role in providing low-complexity video encoder. But, in order to achieve the better rate-distortion performances, most DVC systems need feedback channel for parity bit control. This causes the DVC-based system to have high decoding latency and becomes as one of the most critical problems to overcome for a real implementation. In order to overcome this problem and to accelerate the commercialization of the DVC applications, this paper analyzes an effect of LDPCA frame size for adaptive LDPCA frame-based parity bit request estimations. First, this paper presents the LDPCA segmentation method in pixel-domain and explains the temporal-based bit request estimation method and the spatial-based bit request estimation method using the statistical characteristics between adjacent LDPCA frames. Through computer simulations, it is shown that the better performance and fast decoding is observed specially when the LDPCA frame size is 3168 in QCIF resolution.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.1-8
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• 2018

Recently, the convolutional neural network shows high performance in many computer vision tasks. However, convolutional neural networks require enormous amount of operation, so it is difficult to adopt them in the embedded environments. To solve this problem, many studies are performed on the ASIC or FPGA implementation, where an efficient representation method is required. The fixed-point representation is adequate for the ASIC or FPGA implementation but causes a performance degradation. This paper proposes a separate optimization of representations for the convolutional layers and the batch normalization layers. With the proposed method, the required bit width for the convolutional layers is reduced from 16 bits to 10 bits for the ResNet-50 neural network. Since the computation amount of the convolutional layers occupies the most of the entire computation, the bit width reduction in the convolutional layers enables the efficient implementation of the convolutional neural networks.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.1015-1022
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• 2012

This paper deals with hardware design which unifies MD5 and HAS-160 hash algorithms. Two algorithms get a message with arbitrary length and process message blocks divided into 512 bits each time and output a hash code with a fixed length. MD5 ouputs a hash code of 128 bits and HAS-160 a hash code of 160 bits. The unified hash core designed has 32% of slices overhead compared to HAS-160 core. However, there is only a fixed message buffer space used. The unified hash core which run a step in one clock cycle operates at 92MHz and has performance which digests a message in the speed of 724Mbps at MD5 and 581Mbps at HAS-160 hash mode. The unified hash core which is designed can be applicable to the areas such as E-commerce, data integrity and digital signature.

• Journal of the Korea Society of Computer and Information
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• v.17 no.10
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• pp.89-98
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• 2012

In this paper, we proposed the efficient addressing scheme for improving the performance of routing algorithm by using ZigBee in Smart Grid environment. In a 16-bit address space and the network size of a few thousands, it is very unlikely to suffer from frequent address collisions. In response, we propose an elegant (x, y, z) coordinate axes addressing scheme from divided address space of 16 bit and its routing algorithm. One of disadvantages of (x, y) coordinate axes addressing, however, is that any router may not hold as many children as proposed, since sensor nodes tend to be connected to a geographically nearby router. We also present an adaptive routing algorithm for location-aware routing algorithms, using our addressing scheme. As a result, each node was reduced not only bitwise but also multi hop using the coordinate axes while routing and the effective address assignment and routing is to minimize the average energy consumption of each node in the network.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.2
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• pp.145-154
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• 1991

In this dissertation, the same reading and writing operation of general SRAM, the algonthm and hardware of 8 bit $\times$16 word CAM(Content Addressable Memory) which carry out the parallel that search is presented. The designed CAM chip consists of five functional blocks (CAM cell array, Address Deceden, Address Encoden. Data Selector, Sense Amplifier). The smulation is performed using logic smmulator on Apollo workstation and PSPICE eitcut simulation on PC/AT. The designed CAM was fabricated by 3um CMOS N Well process (ETRI) design nitles and testing was performed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.185-187
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• 2011

최근 선박 및 물류 자동화는 물류 증대와 함께 선박의 운용을 더욱 복잡하게 만들고 있으며, 선박 내부의 통신 장비 및 통신 시스템의 구성 또한 매우 복잡하게 구성되어 있다. 때문에 지금 현재의 통신장비의 내부 통신 프로토콜은 일반적인 RS-422,485 기반의 NMEA-0183과 CAN 통신 기반의 NMEA-2000 기반으로 해상전자장비의 인터페이스 표준으로 법제화 되어있다. 본 논문에서는 가장 일반적인 NMEA-0183 프로토콜을 7-체널의 NMEA-0183 시리얼 통신 데이터를 지원하도록 설계하였으며, 그 외에 SPI 방식의 3-체널 16비트 ADC(Analog Digital Converter)와 SPI 방식의 2-체널 펄스(pulse) 입력을 받을 수 있도록 설계하였다. 특히, 선박용 통신장비의 중요한 7가지로 한정하여 설계하였다. 본 연구의 소형화를 통하여 이동이 가능하도록 하여 그 편리성을 제공하고, 소형 PC 기반의 중앙 모니터링 시스템을 구현하여 다체널 인디케이트 시스템의 효율성을 제시하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.9C
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• pp.831-839
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• 2006

In this paper, we present an exact and general expression involving two-dimensional Gaussian Q-functions for the bit error rate (BER) of hierarchical MPSK with I/Q phase and amplitude imbalances over an additive white Gaussian noise (AWGN) channel. First we derive a BER expression for the k-th bit of hierarchical 4, 8, 16-PSK signal constellations when Gray code bit mapping is employed. Then, from the derived k-th bit BER expression, we present the exact and general average BER expression for hierarchical MPSK with I/Q phase and amplitude imbalances. This result can readily be applied to numerical evaluation for various cases of practical interest in an I/Q unbalanced hierarchical MPSK system, because the one- and two-dimensional Gaussian Q-functions can be easily and directly computed usinB commonly available mathematical software tools.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1210-1217
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• 2004

LILI-II stream cipher is an upgraded version of the LILI-128, one of candidates in NESSIE. Since the algorithm is a clock-controlled, the speed of the keystream data is degraded structurally in a clock-synchronized hardware logic design. Accordingly, this paper proposes a 4-bit parallel LFSR, where each register bit includes four variable data routines for feedback or shifting within the LFSR. furthermore, the timing of the proposed design is simulated using a Max+plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and apply to the Lucent ASIC device (LV160C, 0.13${\mu}{\textrm}{m}$ CMOS ＆ 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13${\mu}{\textrm}{m}$ semiconductor for the maximum path delay below 1.8㎱. Finally, we propose the m-parallel implementation of LILI-II, throughput with 4, 8 or 16 Gbps (m=8, 16 or 32).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.123-130
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• 2016

In this paper, a high-performance arithmetic unit which can efficiently accelerate a number of algorithms for multimedia application was designed. The 3-stage pipelined arithmetic unit can execute 38 operations for complex and fixed-point data by using efficient configuration for four 16-bit by 16-bit multipliers, new sign extension method for carry-save data, and correction constant scheme to eliminate sign-extension in compression operation of multiple partial multiplication results. The arithmetic unit has about 300-MHz operating frequency and about 37,000 gates on 45nm CMOS technology and its estimated performance is 300 MCOPS(Million Complex Operations Per Second). Because the arithmetic unit has high processing rate and supports a number of operations dedicated to various applications, it can be efficiently applicable to multimedia processors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2333-2340
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• 2016

A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz.