• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1126-1132
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• 1999

In this paper, we consider the superposed 16-QAM CDMA system for subband coded (SBC) image transmissions. We divide the SBC image bit into two group according to its significance. First, we investigate the average bit error rate (BER) of the overall system when the significance of bits is ignored. Next, we investigate the optimal signal constellation and processing gain that maximizes the peak signal-to-noise ratio (PSNR) of SBC image, subject to a fixed power and bandwidth constraint. We examine the performance improvement over the conventional equal distane, equal processing gain system, and the equal error protection (EEP) system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.4A
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• pp.189-196
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• 2012

A WAVE(Wireless Access for Vehicular Environment) system is a vehicle communication technology. The system provides the services to prevent vehicle accidents that might occur during driving. Also, it is used to provide various services such as monitoring vehicle management and system failure. However, the scrambler bit operation of WAVE system becomes less efficient in the organizations of software and hardware design because the parallel processing is impossible. Although scrambler algorithm proposed in this paper has different processing speed depending on input data 8 bit, 16 bit, 32 bit, and 64 bit. it improves the processing speed of the operation because it can make parallel processing possible depending on the input unit.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.2
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• pp.59-65
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• 2013

Microprocessors of 8 to 16 bits have become the first step of today's computer development with excellent capability and a lot of those are still used in the educational spots. In this study, execution times of Intel series microprocessors(${\mu}ps$) available to microprocessor systems of 8 to 32 bits are obtained and compared by I/O programs. The compared result showed that execution time related to the instruction cycles of 8 bit 8051 was longer than that of 8 bit 8051 and of 16 bit 8086 by a lot of number of clocks in cases of clock frequencies at 4 MHz and at 12 MHz. In cases of really many using ${\mu}p$ clock frequencies, it showed that execution times of instructions have become faster by the order of 8085, 8086, 8051 and 80386. It can be helped to interface with ${\mu}ps$ for real time control through comparing with execution times of I/O programs by mainly many usable Intel series ${\mu}ps$ in our nation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.11
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• pp.2093-2099
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• 2016

This paper describes a design of crypto-processor that supports multiple block cipher algorithms of PRESENT, ARIA, and AES. The crypto-processor integrates three cores that are PRmo (PRESENT with mode of operation), AR_AS (ARIA_AES), and AES-16b. The PRmo core implementing 64-bit block cipher PRESENT supports key length 80-bit and 128-bit, and four modes of operation including ECB, CBC, OFB, and CTR. The AR_AS core supporting key length 128-bit and 256-bit integrates two 128-bit block ciphers ARIA and AES into a single data-path by utilizing resource sharing technique. The AES-16b core supporting key length 128-bit implements AES with a reduced data-path of 16-bit for minimizing hardware. Each crypto-core contains its own on-the-fly key scheduler, and consecutive blocks of plaintext/ciphertext can be processed without reloading key. The crypto-processor was verified by FPGA implementation. The crypto-processor implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,500 gate equivalents (GEs), and it can operate with 55 MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2465-2473
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• 2012

Recently, as one of low complexity video encoding methods, DVC (Distributed Video Coding) scheme has been actively studied. Most of DVC schemes exploit feedback channel to achieve better coding performances, however, this causes these schemes to have high decoding delay. In order to overcome these, this paper proposes a new fast DVC decoding method using parity-bit request model, which can be obtained by using bit-error rate, sent by encoder with motion vector, which is transmitted through feedback channel by decoder after generating side information. Through several simulations, it is shown that the proposed method improves greatly the decoding speed, compared to the conventional schemes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8A
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• pp.1231-1237
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• 2000

DMT기반 VDSL 시스템에서 채널의 주파수 특성에 따라 각 부채널에 각기 다른 비트를 할당하는 "Bit allocation algorithm"은 DMT기반 시스템의 초기화 과정에 필수적으로 사용되며 초기화 시간을 단축하기위해 이알고리즘의 고속화가 필요하다 기존의 알고리즘인 Chow Campello가제시한 알고리즘들은 ADSL과 같이 부채널수가 적은 응용분야에서는 적용 가능했으나 부채널 수가 ADSL의 16배에 이르는 VDSL과 같은 경우에는 계산량이 과다하기 때문에 실시간 적용이 어렵다. 본 논문에서는 수신단에서 계산된 SNR을 미리 계산된 기준 SNR 값과 비교하는 방법을 이용하여 계산량을 줄인 새로운 비트 할당 알고리즘을 제시한다. 제안된 알고리즘은 기존 알고리즘에서 N.log2N의 연산이 필요한 SNR을 내림차순으로 분류하는 과정을 없앴고 log2 연산 덧셈 및 나눗셈의 연산을 단순한 비교 연산으로 대체함으로서 보다 고속으로 각 부채널에 할당할 비트 수를 계산할수 있다 그리고 제안된 고속 알고리즘을 VDSL 시스템에 적용한 결과 기존의 알고리즘인 Chow 알고리즘과 동일한 성능을 보임을 확이하였다.보임을 확이하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.3
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• pp.248-258
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• 1991

In this paper, ISI cancellation capabilites in the frequency selective fading channels of the equalizer emplouing individual tap LMS(ITLMS) algorithm and of th equalizer using the lattice structure have been investigated through the computer simulations in terms of bit error rate and convergence speed.

• Electronics and Telecommunications Trends
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• v.9 no.4
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• pp.147-155
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• 1994

32비트 이하의 마이크로프로세서를 위한 메모리 시스템을 설계하는 방법에 대하여 체계화하여 고찰하였다. 이를 위하여 메모리 디바이스 선택을 위한 일반 사항과 메모리 시스템 설계 방법에 대하여 서술하고, 이 설계 방법에 따라 16비트 마이크로 프로세서 메모리 시스템 설계 예와 설계된 메모리 시스템의 분석, 메모리 디바이스의 속도 결정 등에 대하여 서술하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.786-792
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• 2016

Camellia was jointly developed by Nippon Telegraph and Telephone Corporation and Mitsubishi Electric Corporation in 2000. Camellia specifies the 128-bit message block size and 128-, 192-, and 256-bit key sizes. In this paper, a modified round operation block which unifies a register setting for key schedule and a conventional round operation block is proposed. 16 ROMs needed for key generation and round operation are implemented using only 4 dual-port ROMs. Due to the use of a message buffer, encryption/decryption can be executed without a waiting time immediately after KA and KB are calculated. The suggested block cipher Camellia algorithm is designed using Verilog-HDL, implemented on Virtex4 device and operates at 184.898MHz. The designed cryptographic core has a maximum throughput of 1.183Gbps in 128-bit key mode and that of 876.5Mbps in 192 and 256-bit key modes. The cryptographic core of this paper is applicable to security module of the areas such as smart card, internet banking, e-commerce and satellite broadcasting.