• Proceedings of the Korean Society of Computer Information Conference
• /
• 2017.01a
• /
• pp.145-146
• /
• 2017

본 논문에서는 CPLD 구조를 고려한 게이트 레벨 글리치 제거 방법에 대해 제안하였다. CPLD는 AND-OR 게이트의 2단 구조를 가진 LE를 기본 구조로 구성되어 있는 소자이다. CPLD로 구현할 회로에 대한 DAG를 CPLD 구조에 맞도록 그래프를 분할하여 매핑가능클러스터를 생성한다. 생성된 매핑가능클러스터는 내부의 글리치와 전체 회로에 대한 글리치 발생 가능성을 검사하여 글리치를 제거한다. AND게이트와 OR게이트를 사용하는 2단 구조는 게이트가 달라 글리치가 발생될 수 있는 가능성을 검사하기 어렵다는 단점이 있어 AND-OR 게이트의 2단 구조와 동일한 구조를 가지고 있으며 게이트가 동일한 NAND 게이트를 이용하여 전체 회로를 변환한 후 글리치 발생여부를 검사함으로서 정확한 글리치 발생 가능성을 제거한다. 실험 결과는 제안 된 알고리즘 [10]과 비교하였다. 소비 전력이 2 % 감소되어 본논문에서 제안한 방법의 효율성이 입증되었다.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.12 no.2
• /
• pp.91-98
• /
• 1998

The current-fed high frequency inverter with separated parallel resonant capacitor is presented in this paper. The analysis of the proposed circuit is generally described by using normalized parameter, and are evaluated characteristics of the circuit.In addition, this paper proves the propriety of theoretical analysis in terms of the experimental waveforms using the switching device MOSFET. In the future, the proposed inverter will expected that it can be practically used as the high frequency power source for induction heating etc.ng etc.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.50 no.1
• /
• pp.45-50
• /
• 2001

With increasing complexity of digital logic circuits, fast and accurate verification of functional behaviour becomes most critical bottleneck in meeting time-to-market requirement. This paper presents several techniques for accelerating a cycle-based logic simulation. The acceleration techniques include parallel pattern logic evaluation, circuit size reduction, and the partition of feedback loops in sequential circuits. Among all, the circuit size reduction plays a critical role in maximizing logic simulation speedup by reducing 50% of entire circuit nodes on the average. These techniques are incorporated into a levelized table-driven logic simulation system rather than a compiled-code simulation algorithm. Finally, experimental results are given to demonstrate the effectiveness of the proposed acceleration techniques. Experimental results show more than 27 times performance improvement over single pattern levelized logic simulation.

• Proceedings of the KIPE Conference
• /
• 2012.07a
• /
• pp.560-561
• /
• 2012

LED는 전기적 규격 측면에서 특정 전압을 넘기지 않게 하기 위해서는 다채널로 분할해야 하는데, SMPS가 어떠한 채널에 맞춰 정전압 정전류 제어를 할 지 알 수 없다. 이를 해결하기위해 LED 구동 회로에 적용되는 LED String 최대전압을 검출하고 검출된 전압에 의해서 컨트롤 하게 되면, LED String의 전압이 각 채널별로 차이가 발생할 때 전압 강하를 최소화 할 수 있다. 또한 최대 전압을 감지하여 LED 전압을 변화하면 효율을 극대화 할 수 있다. 회로 구현을 통해서 이상이 구현 가능한지 타당성을 검증하였다.

• Journal of IKEEE
• /
• v.22 no.3
• /
• pp.800-804
• /
• 2018

This paper presents a novel HF band differential quadrature phase-shift keying (DQPSK) orthogonal frequency-division multiplexing (OFDM) communication system. The system can deliver 3.6 kbps with a bandwidth of about 3 kHz. In a digital modem, OFDM with 32-point fast Fourier transform is used. In the system, each subcarrier uses DQPSK modulation. Hence, a demodulator does not require carrier phase recovery and symbol timing recovery. And, each subcarrier employs CRC error check code individually. By using CRC code for each subcarrier, bit error caused by multipath fading can be recovered simply.

• Journal of Bio-Environment Control
• /
• v.10 no.2
• /
• pp.101-105
• /
• 2001

Plant roots are affected by the root zone environment rather than substrate material itself. It is important to provide a suitable environment for the roots by amending the substrate and adjusting supply of the nutrient solution. In an expanded rice hull substrates, 1.5 L nutrient solution was supplied on each day at different frequency. In rice hull substrate, plant growth and yield were the greatest in the treatment where a 1.5L nutrient solution was supplied as 24 equal aliquots, wheres in perlite substrate plant growth and yield were the greatest in the treatment with 16 aliquots. Nitrogen deficiency symptoms caused by early decomposition of rice hulls by microorganisms was recovered by increasing solution EC from 1.7 to EC 2.0 dS.m$^{-1}$ for 25 days after planting. Plant growth and yield increased in the treatment of Ec 3.0 dS.m$^{-1}$ , but the cause for this increase is not clear.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.1
• /
• pp.224-234
• /
• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that if fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs bu 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.19 no.1
• /
• pp.61-70
• /
• 2008

This paper presents the flexible MEMS transmitter based on flexible printed circuit board or FPCB, which can be transformed to arbitrary shape. The FPCB is suitable to fabricate light weight and small size modules with the help of its thin thickness. Moreover a module based on FPCB can be attached on the arbitrary curved surface due to its flexible enough to be lolled up like paper. In this paper, the flexible MEMS transmitter integrated on FPCB for a short-distance sensor network which is based on orthogonal frequency division multiplexing(OFDM) communication system is proposed. The active device of the proposed flexible MEMS transmitter is fabricated on InGaP/GaAs HBT process which has been used for power amplifier design to take advantages of high linear and high efficient characteristics. Moreover, the passive devices such as the filter and signal lines are integrated and fabricated on the FPCB board. The performance of the fabricated flexible MEMS transmitter is analyzed with EVM characteristics of the output signal.

• The Transactions of the Korea Information Processing Society
• /
• v.3 no.3
• /
• pp.640-654
• /
• 1996

This paper presents a synthesis method for multi-level Reed-Muller circuits using BDDs(Binary Decision Diagrams). The existing synthesis tool for Reed circuits, FACTOR, is not appropriate to the synthesis of large circuits because it uses matrix (map-type) to represent given logic functions, resulting in the exponential time and space in number of imput to the circuits. For solving this problems, a syntheisis method based on BDD is presented. Using BDDs, logic functions are represented compactly. Therefor storage spaces and computing time for synthesizing logic functions were greatly decreased, and this technique can be easily applied to large circuits. Using BDD representations, the proposed method extract best patterns to minimize multi-level Reed Muller circuits with good performance in area optimization and testability. Experimental results using the proposed method show better performance than those using previous methods〔2〕. For large circuits of considering the best input partition, synthesis results have been improved.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.11
• /
• pp.1377-1383
• /
• 2019

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.