• Title/Summary/Keyword: 핫 케리어

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A Study on Characteristics of Wet Oxide Gate and Nitride Oxide Gate for Fabrication of NMOSFET (NMOSFET의 제조를 위한 습식산화막과 질화산화막 특성에 관한 연구)

  • Kim, Hwan-Seog;Yi, Cheon-Hee
    • The KIPS Transactions:PartA
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    • v.15A no.4
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    • pp.211-216
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    • 2008
  • In this paper we fabricated and measured the $0.26{\mu}m$ NMOSFET with wet gate oxide and nitride oxide gate to compare that the charateristics of hot carrier effect, charge to breakdown, transistor Id_Vg curve, charge trapping, and SILC(Stress Induced Leakage Current) using the HP4145 device tester. As a result we find that the characteristics of nitride oxide gate device better than wet gate oxide device, especially hot carrier lifetime(nitride oxide gate device satisfied 30 years, but the lifetime of wet gate oxide was only 0.1 year), variation of Vg, charge to breakdown, electric field simulation and charge trapping etc.

A Study on the Hot-Carrier Effects of p-Channel Poly-Si TFT s (p-채널 Poly-Si TFT s 소자의 Hot-Carrier 효과에 관한 연구)

  • 진교원;박태성;백희원;이진민;조봉희;김영호
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.9
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    • pp.683-686
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    • 1998
  • Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

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A Study on Buffered Deposition Device Structure to Improvement for High Density Chip Realiability (고밀도 칩 신뢰성 개선을 위한 buffered deposition 소자구조에 관한 연구)

  • Kim, Hwan-Seog;Yi, Cheon-Hee
    • Journal of the Korea Society for Simulation
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    • v.17 no.2
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    • pp.13-19
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    • 2008
  • New Buffered deposition is proposed to decrease junction electric field in this paper. Buffered deposition process is fabricated after first gate etch, followed NM1 ion implantation and deposition & etch nitride layer. New Buffered deposition structure has buffer layer to decrease electric field. Also we compared the hot carrier characteristics of Buffered deposition and conventional. Also, we design a test pattern including NMOSFET, PMOSFET, LvtNMOS, High pressure N/PMOSFET, so that we can evaluate DC/AC hot carrier degradation on-chip. As a result, we obtained 10 years hot carrier life time satisfaction.

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