• Proceedings of the Korea Society for Simulation Conference
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• 1997.04a
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• pp.31-35
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• 1997

본 논문에서는 암호화 알고리즘의 하나인 GOST (Government Standard)를 칩으로 구현했을 경우에 차지하는 면적과 속도에 대해 DES와 비교 분석하고, GDES의 구조를 이 용하여 GOST 알고리즘을 빠르게 처리할 수 있도록 설계하였다. 합성한 것을 최종적으로 MAX+plus II를 이용하여 시뮬레이션을 통해 검증하였다.

• The Journal of the Korea Contents Association
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• v.18 no.1
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• pp.10-18
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• 2018

This paper presents a method to resynthesize logic of a programmed FPGA from a bitstream file that is a downloaded file for Xilinx FPGA (Field Programmable Gate Array). It focuses on reconfiguring the LUT (Look Up Table) logic. The bitstream data is compared and analyzed considering various situations and various input variables such as composing other logics using the same netlist or synthesizing the same logic at various positions to find a structure of the bitstream. Based on the analyzed bitstream, we construct a truth table of the LUT by implementing various logic for one LUT. The proposed algorithm extracts the logic of the LUT based on the truth table of the generated LUT and the bitstream. The algorithm determines the input and output pins used to implement the logic in the LUT. As a result, we extract a gate level logic from a bitstream file for the targeted Xillinx FPGA.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.19-25
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• 2017

This paper deals with integer factorization of two prime p,q of SHA-256 secure hash value n for Bit coin mining. This paper proposes an algorithm that greatly reduces the execution time of Pollard's rho integer factorization algorithm. Rho(${\rho}$) algorithm computes $x_i=x^2_{i-1}+1(mod\;n)$ and $y_i=[(y^2_{i-1}+1)^2+1](mod\;n)$ for intial values $(x_0,y_0)=(2,2)$ to find the factor 1 < $gcd({\mid}x_i-y_i{\mid},n)$ < n. It however fails to factorize some particular composite numbers. The algorithm proposed in this paper applies multiple initial values $(x_0,y_0)=(2^k,2^k)$ and ($2^k,2$), $2{\leq}k{\leq}10$ to the existing Pollard's Rho algorithm. As a results, the proposed algorithm achieves both the factorization of all the composite numbers and the reduction of the execution time of Pollard's Rho by 67.94%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.4
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• pp.448-458
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• 2013

In this paper, we present the performance and the experimental results of the adaptive beamformer in the radar system with the planar active array. The study of the adaptive beamformer has already been performed in several literatures, but it is difficult to find the results or examples those are implemented in the actual radar system. Here we employ the adaptive beamformer to the practical radar system with subarray architecture. The performance of beamformer will be demonstrated by modeling and simulation and finally the far-field experimental results.

• Journal of KIISE
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• v.42 no.11
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• pp.1332-1338
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• 2015

Recently, growing attention has been paid to multi-GPU rendering to support real-time high-quality rendering at high resolution. In order to attain high performance in real-time multi-GPU rendering, great care needs to be taken to reduce the overhead of data transfer among GPUs and frame composition. This paper presents a novel multi-GPU algorithm that greatly enhances split frame rendering with implicit query-based synchronization. In order to support implicit synchronization in frame composition, we further present a message queue-based scheduling algorithm. We carried out an experiment to evaluate our algorithm, and found that our algorithm improved rendering performance up to 200% more than previously existing algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3C
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• pp.287-294
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• 2010

MB-OFDM UWB system will adopt LDPC codes to enhance the decoding performance with higher data rates. In this paper, we will consider algorithm and architecture of the LDPC codes in MB-OFDM UWB system. To suggest the hardware efficient LDPC decoder architecture, LLR(log-likelihood-ration) calculation algorithms and check node update algorithms are analyzed. And we proposed the architecture of LDPC decoder for the high throughput application of Wimedia UWB. We estimated the feasibility of the proposed architecture by implementation in a FPGA. The implementation results show our architecture attains higher throughput than other result of QC-LDPC case. Using this architecture, we can implement LDPC decoder for high throughput transmission, but it is 0.2dB inferior to the BP algorithm.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.1
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• pp.39-44
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• 2005

Scheduling for digital system synthesis is assigning each operation in a control/data flow graph(CDFG) to a specific control step without violating precedence relation. It is one of the most important tasks due to its direct influence on the performance of the hardware synthesized. In this paper, we propose a resource-constrained scheduling algorithm. Our algorithm first analyzes the given CDFG to determine the number of functional units of each type, then assigns each operation to a control step while satisfying the constraints. It also tries to improve the solution iteratively by adjusting the number of functional units using the results collected from the previous scheduling. Experiments were performed to test the performance of the proposed algorithm, and results are presented

• Journal of the Korea Society of Computer and Information
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• v.28 no.4
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• pp.1-11
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• 2023

In this paper, instead of using recurrent neural network, we compare a classification performance of time series imaging algorithms using convolution neural network. There are traditional algorithms that imaging time series data (e.g. GAF(Gramian Angular Field), MTF(Markov Transition Field), RP(Recurrence Plot)) in TSC(Time Series Classification) community. Furthermore, we compare STFT(Short Time Fourier Transform) algorithm that can acquire spectrogram that visualize feature of voice data. We experiment CNN's performance by adjusting hyper parameters of imaging algorithms. When evaluate with GunPoint dataset in UCR archive, STFT(Short-Time Fourier transform) has higher accuracy than other algorithms. GAF has 98~99% accuracy either, but there is a disadvantage that size of image is massive.

• Journal of Internet Computing and Services
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• v.24 no.5
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• pp.37-50
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• 2023

In general, PLL or DDS are mainly used as precise and stable frequency synthesis methods. For stable operation, a PWM frequency generation algorithm was designed and implemented using FPGA. This is an algorithm that creates a frequency 8,192 times the target frequency and then performs the D flip-flop 13 times to generate multiple frequencies with a precision of 1 Hz. Using the designed algorithm, it is applied to the Berthing system for stopping trains in station. The applied product was developed and tested against the existing operating system to confirm its superior performance in terms of frequency generation accuracy.

• The Journal of the Acoustical Society of Korea
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• v.19 no.1
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• pp.25-31
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• 2000

In this paper, we proposed an algorithm that used a direct method to set an initial value of Broydon-Fletcher-Goldfarb-Shanno(BFGS) method and, accordingly, conducted an experiment in optimal directivity synthesis of adaptive ultrasonic transducer by point source array. To certify the efficiency of this method, quasi-ideal beam with arbitrary beam width, rotating beam, and multi beam, all with the limited side lobe level -30dB, were chosen to check the problem of directivity synthesis that was formed by point source array in the second dimensional sound field. The numerical calculation results showed that the proposed method performed the directivity synthesis faster than the BFGS method did. In addition, the proposed method showed a good error correction for directivity synthesis, and did not demand the choice of initial value. Finally, it is also shown that the proposed method can be used for the adaptive control that was not possible with the direct method alone.