• Electrical & Electronic Materials
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• v.9 no.5
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• pp.476-482
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• 1996

The multi-dielectric layer SiO$_{2}$/Si$_{3}$N$_{4}$/SiO$_{2}$(ONO) is used to improve electrical capacitance and to scale down the memory device. In this paper, improvement of the capacitance by reducing the bottom oxide thickness in the nitride deposition with load lock(L/L) vacuum system is studied. Bottom oxide thickness under the nitride layer is measured by ellipsometer both in L/L and non-L/L systems. Both results are in the range of 3-10.angs. and 10-15.angs., respectively, independent of the nitride and top oxide thickness. Effective thickness and cell capacitance for SONOS capacitor are in the range of 50-52.angs. and 35-37fF respectively in the case of nitride 70.angs. in L/L vacuum system. Compared with non-L/L system, the bottom oxide thickness in the case of L/L system decreases while cell capacitance increases about 4 fF. The results obtained in this study are also applicable to ONO scaling in the thin bottom oxide region of memory stacked capacitor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2899-2904
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• 2015

This paper introduces about the effect on $I_{DS}-V_{GS}$ characteristic of transistor that interface trap charge is created by damage due to heat in a 3D sequential inverter. A interface trap charge distribution in oxide layer in a 3D sequential inverter is extracted using two-dimensional device simulator. The variation of threshold voltage of top transistor according to the gate voltage variation of bottom transistor is also described in terms of Inter Layer Dielectric (ILD) length of 3D sequential inverter, considering the extracted interface trap charge distribution. The extracted interface trap density distribution shows that the bottom $HfO_2$ layer and both the bottom and top $SiO_2$ layer were relatively more affected by heat than the top $HfO_2$ layer with latest process. The threshold voltage variations of the shorter length of ILD in 3D sequential inverter under 50nm is higher than those over 50nm. The $V_{th}$ variation considering the interface trap charge distribution changes less than that excluding it.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.23-29
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• 2001

The effects of Ti-silicide process on the electrical properties of an analog polysilicon capacitor were investigated. To improve the linearity with the applied voltage both electrodes, which are polysilicon in our device, should have almost same material properties. The doping concentrations of both electrodes need to be high and to have the similar levels. Voltage Coefficient of Capacitance (VCC) is one of the properties to represent the linearity of analog capacitor, and it is related with the material and the structure of capacitor. In this study, it was possible to obtain the lower VCC by siliciding the polysilicon areas of capacitor. This is due to the parasitic capacitance at the interfaces between silicide and polysilicons, resulting the decrease of unit capacitance. However, we assumed the creation of positive oxide charge near the lower polysilicon electrode during the silicide process.