• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11A
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• pp.1059-1067
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• 2006

AODV(Ad-hoc On-demand Distance Vector) routing protocol was devised for use of mobile nodes in Ad-hoc network. When we use the AODV routing protocol in Ad-hoc networks with high mobility, disturbance of optimized route path and link break occur. In order to solve the shortcomings, this paper proposes a new routing protocol in which new routing control messages are added to the existing AODV. The proposed protocol minimizes link break and transmission delay while is able to secure the optimized route path constantly in changes of network topology The performance of the proposed routing protocol was evaluated by using us2 network simulator. The actual Ad-hoc network test bed provides us the most reliable experimental data for Ad-hoc networks. In order to support this experimental environment, the dissertation also developed an efficient embedded system on which AODV routing protocol, NAT, Netfilter can run and other event message can be verified without declining efficiency. The correct operation of AODV routing protocol has been verified in both the Ad-hoc network test bed in which the embedded system was used, and Ad-hoc networks linked with Ethernet backbone network.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2569-2578
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• 2009

Core-A microprocessor is the all-Korean product designed as 32-bit embedded RISC microprocessor developed by KAIST and supported by the Industrial Property Office. This paper analyze Core-A microprocessor architecture and proposes efficient method to interface Core-A microprocessor with coprocessor. To verify proposed interfacing method, the AES cryptography processor that has 128-bit key and block size is used as a coprocessor. Coprocessor and AES are written in Verilog-HDL and verified using Modelsim simulator. It except AES module consists of about 3,743 gates and its maximum operating frequency is about 90Mhz under 0.35um CMOS technology. The proposed coprocessor interface architecture is efficiency to send data or to receive data from Core-A to coprocessor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.9
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• pp.1095-1102
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• 2016

In this paper, we propose a decoding scheme that can apply to a three dimensional turbo product code(TPC) with a single parity check code(SPC). In general, SPC is used an axis with shortest code length in order to maximize a code rate of the TPC. However, SPC does not have any error correcting capability, therefore, the error correcting capability of the three-dimensional TPC results in little improvement in comparison with the two-dimensional TPC. We propose two schemes to improve performance of three dimensional TPC decoder. One is $min^*$-sum algorithm that has advantages for low complexity implementation compared to Chase-Pyndiah algorithm. The other is a modified serial iterative decoding scheme for high performance. In addition, the simulation results for the proposed scheme are shown and compared with the conventional scheme. Finally, we introduce some practical considerations for hardware implementation.

• Journal of Korea Multimedia Society
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• v.3 no.2
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• pp.192-200
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• 2000

8 bit and 16 bit microprocessors are widely used in the small sited control machine. The embedded microprocessors which is integrated on a single chip with the memory and I/O circuit must have simple hardware circuit and high code density. This paper proposes a 16 bit high code density EISC(Extendable Instruction Set Computer) microprocessor. SE1608 has 8 general purpose registers and 16 bit fixed length instruction set which has the short length offset and small immediate operand. By using an extend register and extend flag, the offset and immediate operand in instruction could be extended. SE1608 is implemented with 12,000 gate FPGA and all of its functions have been tested and verified at 8MHz. And the cross assembler, the cross C/C++compiler and the instruction simulator of the SE1608 have been designed and verified. This paper also proves that the code density$.$ of SE1608 shows 140% and 115% higher code density than 16 bit microprocessor H-8300 and MN10200 respectively, which is much higher than traditional microprocessors. As a consequence, the SE1608 is suitable for the embedded microprocessor since it requires less program memory to any other ones, and simple hardware circuit.

• Journal of the Korea Society for Simulation
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• v.25 no.4
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• pp.43-52
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• 2016

Wireless sensor network (WSN) technology has been implemented using commercial off-the-shelf microcontrollers (MCUs), In this paper, we propose a simulation environment to realize the physical evaluation of FPGA-based node by considering vertically cross-layered WSN in terms of physical node device and network interconnection perspective. The proposed simulation framework emulates the physical FPGA-based sensor nodes to interoperate with the NS3 through the runtime infrastructure (RTI). For the emulation and interoperation of FPGA-based nodes, we extend a vendor-providing FPGA design tool from the host computer and a script to execute the interoperation procedures. The standalone NS-3 is also revised to perform interoperation through the RTI. To resolve the different time-advance mechanisms between the FPGA emulation and event-driven NS3 simulation, the pre-simulation technique is applied to the proposed environment. The proposed environment is applied to IEEE 802.15.4-based low-rate, wireless personal area network communication.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.34 no.1
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• pp.21-29
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• 2024

With the development of ICT and network, security management of IT infrastructure that has grown in size is becoming very difficult. Many companies and public institutions are having difficulty managing system and network security. In addition, as the complexity of hardware and software grows, it is becoming almost impossible for a person to manage all security. Therefore, AI is essential for network security management. However, since it is very dangerous to operate an attack model in a real network environment, cybersecurity emulation research was conducted through reinforcement learning by implementing a real-life network environment. To this end, this study applied reinforcement learning to the network environment, and as the learning progressed, the agent accurately identified the vulnerability of the network. When a network vulnerability is detected through AI, automated customized response becomes possible.

• Journal of the Korea Society for Simulation
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• v.22 no.4
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• pp.39-47
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• 2013

Simulation based Battle Experimentation is to examine the readiness for a battle using simulation technology. It heavily relies on the weapon systems modeling and simulation. To analyze the characteristics and complexity of the weapon systems in the experiment, the modeling & simulation environment has to be able to break down the system of systems into components and make the use of high fidelity components such as real hardware in simulation. In that sense, the modular and hierarchical structure of DEVS (Discrete EVent System Specification) framework provides potentials to meet the requirements of the battle experimentation environment. This paper describes the development of the DEVS integrated development environment for Simulation based Battle Experimentation. With the design principles of easy, flexible, and fast battle simulation, the newly developed battle experimentation tool mainly consists of 3 parts - model based graphical design tool for making DEVS models and linking them with external simulators easily through diagrams, the experiment plan tool for speeding up a statistic analysis, the standard components model libraries for lego-like building up a weapon system. This noble simulation environment is to provide a means to analyze complex simulation based experiments with different levels of models mixed in a simpler and more efficient way.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.107-116
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• 2009

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nanoelectronic devices which will inherit the throne of CMOS which is the domineering implementation technology for large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors is proposed. After the gate and interconnect structures of. the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit adder, a bit-serial adder, and an ALU bit-slice. For each design, the digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• Journal of Satellite, Information and Communications
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• v.12 no.3
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• pp.108-113
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• 2017

The OBCP called 'operator on board' is that of a procedure to be executed on-board, which can be easily be loaded, executed, and also replaced, without modifying the remainder of the FSW. The use of OBCP enhances the on-board autonomy capabilities and increases the robustness to ground stations outages. The OBCP engine which is the core module of OBCP component in the FSW interprets and executes of the procedures based on script language written using a high-level language, possibly compiled, and it is relying on a virtual machine of the OBCP engine. FSW team in KARI has studied OBCP since 2010 as FSW team's internal projects, and made some OBCP engines such as Java KVM, RTCS/C and KKOMA on ERC32 processor target only for study. Recently we have been studying ESA's OBCP standard and implementing Lua and MicroPython on LEON2-FT/AT697F processor target as the OBCP engine. This paper presents the design and implementation of Lua for the OBCP engine on AT697F processor with VxWorks RTOS, and describes the evaluation result and performance of the OBCP engine.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.1
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• pp.42-56
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• 2002

It is possible but not efficient to model and simulate asynchronous microprocessors with the existing HDLs(HARDware Description Languages) such as VHDL or Verilog. The reason it that the description becomes too complex. and also the simulation time becomes too long to explore the design space. Therefore it is necessary to establish a methodology and develop a tool for modeling the handshake protocol of asynchronous microprocessors very easily and simulating it very fast. Under this objective an efficient CAD(Computer Aided Design) tool SLEDS(System Level Event-Driven Simulator) was developed which can evaluate performance of a processor through modeling with a simple description an simulating with event driven engine in the system level. The ultimate goal in the tool SLEDS is to fin the optimal conditions for a system to produce high performance by balancing the delay of each module in the system. Besides SLEDS aims at verifying the design through comparing the expected results with the actual ones by performing the defined behavior.