• Aerospace Engineering and Technology
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• v.11 no.1
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• pp.49-56
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• 2012

The flight software monitors the status of the satellite and performs attitude control and its own mission. Due to the operating environments and its uniqueness, the high level of reliability is required for the flight software. To this end, a variety of activities to meet the given requirements and improve the safety and reliability are made during the development of flight software. A variety of development environments should be provided to support execution of flight software on hardware or satellite simulator and dynamic verification of flight software through command/telemetry interface. The satellite flight software team has been developing the IVF to be applied to various satellite projects more effectively and to improve the reliability of flight software. In this paper, the design and configuration method of IVF for the effective verification of flight software is introduced.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.8
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• pp.741-751
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• 2000

To achieve high performance by exploiting instruction level parallelism aggressively in superscalar processors, it is necessary to overcome the limitation imposed by control dependences and data dependences which prevent instructions from executing parallel. Value prediction is a technique that breaks data dependences by predicting the outcome of an instruction and executes speculatively its data dependent instruction based on the predicted outcome. In this paper, a hybrid value prediction scheme with dynamic classification mechanism is proposed. We design a hybrid predictor by combining the last predictor, a stride predictor and a two-level predictor. The choice of a predictor for each instruction is determined by a dynamic classification mechanism. This makes each predictor utilized more efficiently than the hybrid predictor without dynamic classification mechanism. To show performance improvements of our scheme, we simulate the SPECint95 benchmark set by using execution-driven simulator. The results show that our scheme effect reduce of 45% hardware cost and 16% prediction accuracy improvements comparing with the conventional hybrid prediction scheme and two-level value prediction scheme.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.44 no.5
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• pp.416-422
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• 2016

This paper presents preliminary performance analysis of a satellite formation flying testbed, which is under development by Astrodynamics and Control Laboratory, Department of Astronomy, Yonsei University. A model reference adaptive controller (MRAC) with a first-order reference model is chosen to enhance the response of reaction wheel system which is subject to uncertainties caused by unmodelled dynamics and measurement noise. In addition, an on-line parameter estimation (OPE) technique based on the least square is combined to eliminate the effect of angular measurement noise by estimating the moment of inertia. Both numerical simulations and hardware experiments with MRAC support the effectiveness and applicability of the adaptive control scheme, which maintains the tracking error below $0.25^{\circ}$ for the entire time span. However, the high frequency control input generated in hardware experiment strongly suggests design modifications to reduce the effect of deadzone.

• Journal of the Korea Society of Computer and Information
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• v.13 no.3
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• pp.45-55
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• 2008

Due to the increasing complexity of embedded system design, automatic code generation of embedded software and hardware-software co-design methodologies are gaining great interest from industries and academia. Such an automatic design methodologies are always demanding a formal system specification languages for defining designer's idea clearly and precisely. In this paper, we propose automatic embedded C code generation from SDL (Specification and Description Language, ITU-T recommended the SDL as a standard system description language) with considering a real-time uC/OS-II operating system. Our automatic embedded C code generator is expected to provide a fast specification, verification and performance evaluation platform for embedded software designs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1858-1865
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• 2007

In this paper, we introduce the design and implementation of satellite IP modem. The designed satellite IP modem shows the performance of 0.2% overhead, BER=10-5 when Eb/No=6dB, frequency offset of 8KHz, data rate up to 1536Kbps, $F_{if}=140MHz$. The designed system is verified through software simulation and then implemented with MPC86x communication processor, TMS320C6416 DSP, and Altera FPGA. Since each hardware unit is implemented in daughter board for modularity, we can reduce the development time and easily improve the performance with using better processor. Linux is used for embedded OS because it shows better performance in IP manipulation multitask processing, and hardware control through device driver. The implemented system is tested and verified with channel simulator. Since the proposed IP modem shows small size and light weight, that can be used anywhere with easy if you need IP environment.

• Journal of IKEEE
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• v.25 no.1
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• pp.180-192
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• 2021

One widely used algorithm for image recognition and pattern detection is the convolution neural network (CNN). To efficiently handle convolution operations, which account for the majority of computations in the CNN, we use hardware accelerators to improve the performance of CNN applications. In using these hardware accelerators, the CNN fetches data from the off-chip DRAM, as the massive computational volume of data makes it difficult to derive performance improvements only from memory inside the hardware accelerator. In other words, data communication between off-chip DRAM and memory inside the accelerator has a significant impact on the performance of CNN applications. In this paper, a simulator for the CNN is developed to analyze the main memory or DRAM access with respect to the size of the on-chip memory or global buffer inside the CNN accelerator. For AlexNet, one of the CNN architectures, when simulated with increasing the size of the global buffer, we found that the global buffer of size larger than 100kB has 0.8x as low a DRAM access count as the global buffer of size smaller than 100kB.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.153-164
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• 2010

A program consumes energy by executing its instructions. The amount of cosumed power is mainly proportional to algorithm complexity and it can be calculated by using complexity information. Generally, the complexity of a S/W is estimated by the microprocessor simulator. But, the simulation takes long time why the simulator is a software modeled the hardware and it only provides the information about computational complexity quantitatively. In this paper, we propose a complexity estimation method of analysis of S/W on source code level and produce the complexity metric mathematically. The function-wise complexity metrics give the detailed information about the calculation-concentrated location in function. The performance of the proposed method is compared with the result of the gate-level microprocessor simulator 'SimpleScalar'. The used softwares for performance test are $4{\times}4$ integer transform, intra-prediction and motion estimation in the latest video codec, H.264/AVC. The number of executed instructions are used to estimate quantitatively and it appears about 11.6%, 9.6% and 3.5% of error respectively in contradistinction to the result of SimpleScalar.

• Journal of Astronomy and Space Sciences
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• v.26 no.1
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• pp.99-110
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• 2009

The main purpose of the current research is to developments a real-time Hardware In-the-Loop (HIL) simulation testbed for the satellite formation flying navigation and orbit control. The HIL simulation testbed is integrated for demonstrations and evaluations of navigation and orbit control algorithms. The HIL simulation testbed is composed of Environment computer, GPS simulator, Flight computer and Visualization computer system. GPS measurements are generated by a SPIRENT GSS6560 multi-channel RF simulator to produce pseudorange, carrier phase measurements. The measurement date are transferred to Satrec Intiative space borne GPS receiver and exchanged by the flight computer system and subsequently processed in a navigation filter to generate relative or absolute state estimates. These results are fed into control algorithm to generate orbit controls required to maintain the formation. These maneuvers are informed to environment computer system to build a close simulation loop. In this paper, the overall design of the HIL simulation testbed for the satellite formation flying navigation and control is presented. Each component of the testbed is then described. Finally, a LEO formation navigation and control simulation is demonstrated by using virtual scenario.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.4
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• pp.476-483
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• 2014

This paper describes the operational analysis results of the bipolar DC distribution system coupled with the distributed generators. The energy management for AC/DC power trade and the operational principle of distributed generators and energy storages were first analyzed by computer simulation with PSCAD/EMTDC software. After then a hardware simulator for the bipolar DC distribution system was built, which is composed of the grid-tied three-level inverter, battery storage, super-capacitor storage, and the voltage balancer. Various experiments with the hardware simulator were carried out to verify the operation of bipolar DC distribution system. The developed simulator has an upper-level controller which operates in connection with the controllers for each distributed generator and the battery energy storage based on CAN communication. The developed hardware simulator are possible to use in designing the bipolar DC distribution system and analyzing its performance experimentally.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.10
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• pp.4794-4800
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• 2012

Many researches have been performed to resist buffer overflow attacks. However, the attack still poses one of the most important issue in system security field. It is because programmers are using library functions containing security hole and once buffer overflow vulnerability has been found, the security patches are distributed after the attacks are widely spreaded. In this paper, we propose a new cache level return address stack architecture for resisting buffer overflow attack. We implemented our hardware onto SimpleScalar simulator and verified its functionality. Our circuit can overcome the various disadvantages of previous works with small overhead.