• Korean Security Journal
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• no.36
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• pp.255-292
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• 2013

Burglary (also called breaking and entering and sometimes housebreaking) is a crime, the essence of which is illegal entry into a building for the purposes of committing an offence. It is one of the most common types of crime and also a serious issue for every society. A house that is left insecure is an accessible and attractive target for burglars and therefore burglary resistance test & certification system for doors and windows has been developed in many countries. This paper explores several advanced foreign burglary resistance test/certifcation cases (the British SBD, the Dutch KOMO SKH/SKG, the Japanese CP mark, the Australian Standard Certification) for security products and domestic test/certification systems for fire safety products as a comparative study so that any improvement points can be gained for South Korea in the field of security product performance. The comparative analysis results show that South Korea is far behind the security product certification system and needs a lot of improvement in the system by benchmarking foreign cases. The domestic test/certification systems for fire safety products also give some insights for burglary-related security products' performance certification system in Korea. Overall, the need for relevant rules and regulations, the establishment of standards regarding testing and certification, including certified security +hardware product in building security certification system, performance testing as well as production testing (i.e. quality management system evaluation), the basic competency of testers, incentive system for certified/high quality security products were suggested in order to make an optimal model for the security production performance testing and certification system in Korea.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.4
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• pp.10-16
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• 2012

For high speed visual inspection in semiconductor industries, it is essential to acquire two-dimensional images on regions of interests with a large field of view (FOV) and a high resolution simultaneously. In this paper, an imaging system is newly proposed to achieve high quality image in terms of precision and FOV, which is composed of single lens, a beam splitter, two camera sensors, and stereo image grabbing board. For simultaneously acquired object images from two camera sensors, Zhang's camera calibration method is applied to calibrate each camera first of all. Secondly, to find a mathematical mapping function between two images acquired from different view cameras, the matching matrix from multiview camera geometry is calculated based on their image homography. Through the image homography, two images are finally registered to secure a large inspection FOV. Here the inspection system of using multiple images from multiple cameras need very fast processing unit for real-time image matching. For this purpose, parallel processing hardware and software are utilized, such as Compute Unified Device Architecture (CUDA). As a result, we can obtain a matched image from two separated images in real-time. Finally, the acquired homography is evaluated in term of accuracy through a series of experiments, and the obtained results shows the effectiveness of the proposed system and method.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.592-607
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• 2006

This paper proposes a technique to select processors and hardware IPs and to map the tasks into the selected processing elements, aming to achieve high performance with minimal system cost when multitask applications with real-time constraints are run on a multicore SoC. Such technique is called to 'Hardware-Software Cosynthesis Technique'. A cosynthesis technique was already presented in our early work [1] where we divide the complex cosynthesis problem into three subproblems and conquer each subproblem separately: selection of appropriate processing components, mapping and scheduling of function blocks to the selected processing component, and schedulability analysis. Despite good features, our previous technique has a serious limitation that a task monopolizes the entire system resource to get the minimum schedule length. But in general we may obtain higher performance in multitask multicore system if independent multiple tasks are running concurrently on different processor cores. In this paper, we present two mapping techniques, task mapping avoidance technique(TMA) and task mapping pinning technique(TMP), which are applicable for general cases with diverse operating policies in a multicore environment. We could obtain significant performance improvement for a multimedia real-time application, multi-channel Digital Video Recorder system and for randomly generated multitask graphs obtained from the related works.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• The KIPS Transactions:PartB
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• v.11B no.3
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• pp.327-336
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• 2004

For visual inspection system in real industrial environment, it is one of most important tasks to design fast and stable pattern matching algorithm. This paper presents an edge-based point correlation algorithm avoiding full search in visual inspection system. Conventional algorithms based on NGC(normalized gray-level correlation) have to overcome some difficulties for applying to automated inspection system in factory environment. First of all, NGC algorithms need high time complexity and thus high performance hardware to satisfy real-time process. In addition, lighting condition in realistic factory environments if not stable and therefore intensity variation from uncontrolled lights gives many roubles for applying directly NGC as pattern matching algorithm in this paper, we propose an algorithm to solve these problems from using thinned and binarized edge data and skipping full point search with edge-map analysis. A point correlation algorithm with the thinned edges is introduced with image pyramid technique to reduce the time complexity. Matching edges instead of using original gray-level pixel data overcomes NGC problems and pyramid of edges also provides fast and stable processing. All proposed methods are preyed from experiments using real images.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06a
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• pp.110-112
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• 2012

정형기법은 소프트웨어 및 하드웨어 시스템의 요구사항을 모순, 모호함 없이 정확하게 명세하고 검증할 수 있는 방법으로, 안전성이 중요한 소프트웨어에 많이 적용되어 반드시 보장되어야 할 속성을 소프트웨어가 만족하는지 확인하는데 사용되고 있다. 본 논문은 정형기법 커뮤니티에서 선정한 여러 도전 과제 중 하나인 인공 심장 박동기(pacemaker)를 실시간 속성을 표현할 수 있는 정형기법 도구인 UPPAAL을 사용하여 모델링하고 주요 속성을 검증하였다. 이를 통해 실시간 속성으로 인해 명세 및 검증하기 힘든 소프트웨어에 정형기법을 적용하여 안전성을 확인할 수 있음을 보인다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2000.11b
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• pp.95-100
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• 2000

본 논문에서는 디지털 TV 방송 스트림을 분석, 검증하기 위한 시스템을 PC 상에서 소프트웨어 기반으로 구현하였다. 저장되어 있는 MPEG-2 트란스포트 스트림(transport stream, TS) 파일을 입력으로 받으며 별도의 하드웨어 장치를 사용하지 않는다. 이 분석기는 PSI(program specific information), TS 섹션, TS 헤더 등 기본 내용뿐만 아니라, TS 패킷들을 오디오, 비디오, PCR(program clock reference), 부가 데이터, 널(null) 패킷 등으로 구분하여 그래픽 사용자 인터페이스 통하여 보여 준다. 또한, 현재 표시되고 있는 TS 패킷과 가장 가까운 I 프레임를 디스플레이 해줌으로써 비트스트림 상의 오류 부분과 실제 영상과 쉽게 매칭시킬 수 있도록 해 준다. 본 논문의 분석기는 MPEG-2 비트스트림 적합성 검사 기능도 제공하며, 데이터 방송을 위한 여러 가지 부가 데이터를 MPEG-2 기본 스트림에 삽입하는 기능도 갖고 있다. 본 논문의 분석기를 이용함으로써 저비용으로 방송 스트림을 분석, 검증할 수 있을 뿐만 아니라, 실험실 연구를 위한 데이터 방송용 비트스트림을 저비용으로 제작할 수 있다.

• The Magazine of the IEIE
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• v.30 no.3
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• pp.309-309
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• 2003

본 논문은 MAP(Maximum A Posteriori) 복호 알고리즘을 이용한 MAP Decoder의 설계에 관해 다룬다. 채널코딩기법은 채널을 통해서 디지털 정보를 전송할 때 신뢰성을 제공하기 위해서 사용되어진다. 즉 수신 단에서 수신된 정보의 오류를 검사하고 수정하기 위한 목적으로 송신 단에서는 디지털 정보에 부가 정보를 첨가해서 전송하게 된다. 그래서 무선 이동 통신에서 성능이 우수한 채널코딩기법은 우수한 통신 품질을 위해서는 필수적이라고 할 수 있다. 최근에 Shannon의 한계에 매우 근접한 성능으로 많이 알려진 오류정정부호로 터보코드가 발표되었고 많은 연구가 진행되고 있다. 터보코드의 부호기로는 RSC(Recursive Systematic Convolutional) 코드가 사용되며 복호 알고리즘으로는 주로 MAP 복호 알고리즘을 사용한다. 본 논문에서 제안된 MAP 복호기는 하드웨어로 구현하기 위해서 변형된 LOG-MAP 복호 알고리즘을 이용하였고 터보디코더의 반복 복호에 이용할 수 있다.

• The Magazine of the IEIE
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• v.30 no.3
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• pp.95-105
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• 2003

본 논문은 MAP (Maximum A Posteriori)복호 알고리즘을 이용한 MAP Decoder의 설계에 관해 다룬다. 채널코딩기법은 채널을 통해서 디지털 정보를 전송할 때 신뢰성을 제공하기 위해서 사용되어진다. 즉 수신 단에서 수신된 정보의 오류를 검사하고 수정하기 위한 목적으로 송신 단에서는 디지털 정보에 부가 정보를 첨가해서 전송하게 된다. 그래서 무선 이동 통신에서 성능이 우수한 채널코딩기법은 우수한 통신 품질을 위해서는 필수적이라고 할 수 있다. 최근에 Shannon의 한계에 매우 근접한 성능으로 많이 알려진 오류정정부호로 터보코드가 발표되었고 많은 연구가 진행되고 있다. 터보코드의 부호기로는 RSC (Recursive Systematic Convolutional) 코드가 사용되며 복호 알고리즘으로는 주로 MAP 복호 알고리즘을 사용한다. 본 논문에서 제안된 MAP 복호기는 하드웨어로 구현하기 위해서 변형된 LOG-MAP 복호 알고리즘을 이용하였고 터보디코더의 반복 복호에 이용할 수 있다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1040-1048
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• 1987

We propose a hardware architecture called Multiring which is applicable for various geometrical operations on rectilinear objects such as design rule checking in VLSI layout and many image processing operations including noise suppression and coutour extraction. It has both a fast execution speed and extremely high flexibility. The whole architecture is mainly divided into four parts` I/O between host and Multiring, ring memory, linear processor array and instruction decoder. Data transmission between host and Multiring is bit serial thereby reducing the bandwidth requirement for teh channel and the number of external pins, while each row data in the bit map stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 16 basic instructions such as Boolean (AND, OR, NOT, and Copy), geometrical(Expand and Shrink), and I/O operations each ring cycle, which gives Multiring maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of Multiring was confirmed by successfully running a software simulator having one-to-one structural correspondence to the Multiring hardware.