• Journal of Korea Multimedia Society
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• v.2 no.4
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• pp.476-489
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• 1999

HW/SW codesign is integrated design of systems implemented using both hardware and software components. Many design tools has been developed to support this new paradigm, so far. Current codesign tools are not widely used as been expected because of variety problems - rapidly evolving technology, platform dependency, absence of standard specification method, inconsistent user interface, varying target system, different functionality In this paper, we propose a web-based distributed HW/SW codesign environment to remedy this kinds of problem. Our codesign environment has object-based 3 tier client/server architecture. It supports collaborative workspace through session service. Fully object-oriented design of user interface(OOUI) enables easy extension without change of user Interface. Furthermore it contains transaction server and security server for efficient and safe transfer of design data. To show a validity of our design, we developed prototype of web-based HW/SW codesign environment called WebCEDA. Our model of HW/SW codesign can be used for web-based generic CAD tools.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.2
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• pp.287-294
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• 2017

Recently, many kinds of TV contents based on multimedia need transmission systems without the saved. In this study, we develop the streaming device and smart app to transmit and play without store for multimedia contents such a broadcasting, internet, VOD, video, and animation. To do this, we compare and analysis main CPU products, broadcasting tuners and interfaces for streaming sources, and memory products. We then design and implement the streaming device which supports 30fps@FHD H.264 decoding and streaming, and multimedia sources with more than three. We develop the software for these requirements. Thissystemis useful to support billing service for multimedia contents.

• Journal of Broadcast Engineering
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• v.21 no.5
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• pp.803-815
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• 2016

In this paper, we design a direct radio frequency (RF) sampling receiver for multiband GNSS signals and demonstrate its performance. The direct RF sampling is a technique that does not use an analog mixer, but samples the passband signal directly, and all receiver processes are done in digital domain, whereas the conventional intermediate frequency (IF) receiver samples the IF band signals. In contrast to the IF sampling receiver, the RF sampling receiver is less complex in hardware, reconfigurable, and simultaneously converts multiband signals to digital signals with an analog-to-digital (AD) converter. The reconfigurability and simultaneous reception are very important in military applications where rapid change to other system is needed when a system is jammed by an enemy. For simultaneous reception of multiband signals, the sampling frequency should be selected with caution by considering the carrier frequencies, bandwidths, desired intermediate frequencies, and guard bands. In this paper, we select a sampling frequency and design a direct RF sampling receiver to receive multiband global navigation satellite system (GNSS) signals such as GPS L1, GLONASS G1 and G2 signals. The receiver is implemented with a commercial AD converter and software. The receiver performance is demonstrated by receiving the real signals.

• Journal of the HCI Society of Korea
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• v.1 no.2
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• pp.1-8
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• 2006

This paper presents a development of new haptic API (Application Programming Interface) that is called K-$Touch^{TM}$ haptic API. It is designed in order to allow users to interact with objects by kinesthetic and tactile modalities through haptic interfaces. The K-$Touch^{TM}$ API would serve two different types of users: high level programmers who need an easy to use haptic API for creating haptic applications and researchers in the haptic filed who need to experiment or develop with new devices and new algorithms while not wanting to re-write all the required code from scratch. Since the graphic hardware based kinesthetic rendering algorithm implemented in the K-$Touch^{TM}$ API is different from any other conventional kinesthetic algorithms, this API can provide users with haptic interaction for various data representations such as 2D, 2.5D depth(height field), 3D polygon, and volume data. In addition, this API supports kinesthetic and tactile interaction simultaneously in order to allow users with realistic haptic interaction. With a wide range of applicative characteristics, therefore, it is expected that the proposed K-$Touch^{TM}$ haptic API will assists to have deeper recognition of the environments, and enhance a sense of immersion in environments. Moreover, it will be useful development toolkit to investigate new devices and algorithms in the haptic research field.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2320-2322
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• 2004

전자제어식 미끄럼방지 제동장치 (ABS, Antilock Brake System)는 차량의 급제동시 발생할 수 있는 바퀴의 슬립을 방지하여 차량의 제동거리를 단축시키고 주행 성능을 향상시키는 차량 내 안전장치이다. 지난 몇 년 동안 공압식 제동시스템을 사용하는 대형차량에 적합한 미끄럼방지 제동 제어기를 연구해 왔다. 이 제어기는 바퀴의 슬립율과 그 변화량을 이용한 제어 법칙을 유도하여, 제어 파라미터로 사용하고 있다. 이러한 제어 파라미터의 튜닝에는 맡은 반복적인 실험이 요구된다. 이러한 요구에 부응하기 위하여 차량의 제동을 실시간으로 모사 할 수 있는 HILS (Hardware In-the Loop Simulation) 시스템을 개발, 구축하였다. 개발 HILS는 공압식 브레이크 시스템 및 14 자유도를 가지는 차량 동역학 모델 및 타이어-바퀴 동역학을 소프트웨어 모델로 사용하고, 개발 중인 전자제어식 미끄럼 방지 제동 제어기를 하드웨어로 사용하여, 바퀴속도 센서 신호 모의 장치 및 공압 엑추에이터 모의 신호등의 인터페이스 장치를 사용하여 제동중인 차량의 상태를 실시간으로 시뮬레이션 및 감시할 수 있다. 이 개발 HILS를 이용하여 제동 제어기의 제어 파라미터의 튜닝을 짧은 시간에 성공적으로 끝낼 수 있었을 뿐만 아니라, HILS 실험을 마친 제어기는 미끄럼 방지 제동 시험장에서 실차 주행 시험을 무사히 마침으로써, 개발 기간과 비용을 절감할 수 있는 하드웨어를 이용하는 시뮬레이션의 효용성을 간접적으로 증명하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.137-140
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• 2013

Conventionally embedded devices used simple operating system (OS); however, the number of embedded devices using Linux as OS is increasing to keep up with hardware's performance improvement and customer's various needs. While embedded devices using Linux can take advantage of expandability, generality, portability, Linux's flexibility nature may cause undesirable overheads because of its increased complexity. One such overhead makes boot stage optimization essential in most embedded systems, where many features are redundant and possible to be removed or reconfigured. This paper applies well-known software optimization technique for Linux's boot stage to an CLM9722 DTK, measures the results, and studies about limitation of such techniques from hardware dependancy on the standard framework of Linux. The booting time from power-on until completion were decreased by 33% approximately.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.6 no.1 s.12
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• pp.58-71
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• 2007

The disabled and elderly people have a wide variety of functional impairments. By disability and elderly user group definition, identification of users needs and specification of content requirements were studied. Existing technologies including location, navigation and information exchange devise and communication systems were analyzed to design proper integrated system for indoor and outdoor uses. There are two types of services considered in the project: assisted living services(ALS) including health and emergency needs and assisted mobility services(AMS) with transportation needs. To develop each content, content identification and requirements was studied through interviews and expert consultations. System requirements and specification using usecase technique for disabled and elderly people are discussed.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.5
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• pp.201-208
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• 2008

An active RFID system has the advantages of a long identification distance and a good identification rate as well as overcoming the passive RFID's drawback such as the lowering of identification rate on metal materials. So, the development of an active RFID system has been gradually increasing in harbor logistics and the national defense area. On the other hand, some identification failures between products developed under the same standards have been reported, and there are difficulties in evaluating the interoperability between developed Products and standard conformance test because an accurate evaluation method and equipment has not been established at the international level. Motivated by these, this study presents a realization of the hardware and software of emulator to evaluate the standard conformance of an active RFID system, Performance of the designed system are then analyzed by means of simulations of Matlab/Simulink, and the applicability of the emulator is verified by evaluating the standard conformance of a real active RFID tag.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5389-5396
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• 2012

In this paper, an optimized residual data decoder architecture is proposed to improve the performance in H.264/AVC. The proposed architecture is an integrated architecture that combined parallel inverse transform architecture and parallel inverse quantization architecture with common operation units applied new inverse quantization equations. The equations without division operation can reduce execution time and quantity of operation for inverse quantization process. The common operation unit uses multiplier and left shifter for the equations. The inverse quantization architecture with four common operation units can reduce execution cycle of inverse quantization to one cycle. The inverse transform architecture consists of eight inverse transform operation units. Therefore, the architecture can reduce the execution cycle of inverse transform to one cycle. Because inverse quantization operation and inverse transform operation are concurrency, the execution cycle of inverse transform and inverse quantization operation for one $4{\times}4$ block is one cycle. The proposed architecture is synthesized using Magnachip 0.18um CMOS technology. The gate count and the critical path delay of the architecture are 21.9k and 5.5ns, respectively. The throughput of the architecture can achieve 2.89Gpixels/sec at the maximum clock frequency of 181MHz. As the result of measuring the performance of the proposed architecture using the extracted data from JM 9.4, the execution cycle of the proposed architecture is about 88.5% less than that of the existing designs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.