• Title/Summary/Keyword: 프로세서간 통신

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Adaptive Online Processor Management Algorithms for QoS sensitive Multimedia Data Communication (다양한 형태의 멀티미디어 데이터를 위한 통신 프로세서의 효율적 관리 방법에 대한 연구)

  • Kim, Sung-Wook;Kim, Sung-Chun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.1B
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    • pp.17-21
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    • 2007
  • In this paper, we propose new on-line processor management algorithms that manage heterogeneous multimedia services while maximizing energy efficiency. These online management mechanisms are combined in an integrated scheme for higher system performance and energy efficiency. The most important feature of our proposed scheme is its adaptability, flexibility and responsiveness to current network conditions. Simulation results clearly indicate the superior performance of our proposed scheme to strike the appropriate performance balance between contradictory requirements.

Efficient Fault-Tolerant Multicast On Hypercube Multicomputer System (하이퍼 큐브 컴퓨터에서 효과적인 오류 허용 다중전송기법)

  • 명훈주;김성천
    • Proceedings of the Korean Information Science Society Conference
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    • 2000.04a
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    • pp.612-614
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    • 2000
  • 하이퍼큐브의 성능을 좌우하는 중요한 요소 중 하나가 프로세서간의 통신이다. 그리고 병렬 컴퓨터에서 프로세서의 수가 증가함에 따라, 구성요소들이 오류가 날 확률도 높아졌다. 이러한 이유로, 오류 난 구성요소들이 있어도 다중 전송이 가능하게 효율적으로 설계하는 것이 중요하다. 본 논문에서는 최근에 제안된 완전 도달성 정보와 새로 추가한 국지적 정보를 이용해서 라우팅 알고리즘을 제안하고, 이것을 바탕으로 다중 전송 성공률이 높은 새로운 다중 전송 알고리즘을 제안하였다. 시뮬레이션을 통하여 제안한 기법은 기존의 기법 보다 통신량의 차이는 거의 없으면서, 다중 전송 성공률이 목적지 노드 수에 따라 5~15% 가량 향상시킬 수 있었다.

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Efficient task allocation algorithms for reducing processors on real-time multiprocessor system (실시간 다중프로세서 환경에서 프로세서 수의 감소를 위한 효율적인 타스크 배치방식)

  • 신명호;이정태;박승규
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.11
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    • pp.2801-2809
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    • 1996
  • Scheduling problems in real-time systems are known to be NP-hard. the heuristic approaches aregenerally aplied to solve a certain class of systems. One of such cases is to allocate periodic tasks to multiprocessors while the moethod assures the requirement of the deadine constraints of real-time systems. The study on the allocation of periodic taks includes RMNF, RMFF, FFDUF and Next-Fit-M algorithms, which make a set of task grups first and then allocate to processors. This papre proposes the various algorithms which are based on the Next-Fit-M. To analyze the four proposed methods, simulation was carried on, in which the sample tasks are randomly generated with the various time intervals. The proposed algorithms reduce the number of processors compared with the conventional methods.

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A study on the Processor of City construction and u-City business (도시건설사업과 u-City 사업 프로세스)

  • Yoo, Jae-Duck;Shin, Hyun-Sik
    • The Journal of the Korea institute of electronic communication sciences
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    • v.4 no.4
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    • pp.287-292
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    • 2009
  • u-City business is IT projects and City development processor which be coupled to the city development in the planning stages, and u-City planning and design reflecting at that stages can be built efficiently, and cost savings can be. This paper study on how to link between City construction processor and u-City business processor, especially u-City business for success, the key step of the USP (u -City Strategic Planning) be studied.

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A Performance Study of Embedded Multicore Processor Architectures (임베디드 멀티코어 프로세서의 성능 연구)

  • Lee, Jongbok
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.13 no.1
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    • pp.163-169
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    • 2013
  • Recently, the importance of embedded system is growing rapidly. In-order to satisfy the real-time constraints of the system, high performance embedded processor is required. Therefore, as in general purpose computer systems, embedded processor should be designed as multicore architecture as well. Using MiBench benchmarks as input, the trace-driven simulation has been performed and analyzed for the 2-core to 16-core embedded processor architectures with different types of cores from simple RISC to in-order and out-of-order superscalar processors, extensively. As a result, the achievable performance is as high as 23 times over the single core embedded RISC processor.

Implementation of 40 Gb/s Network Processor of Wire-Speed Flow Management (40 Gb/s 실시간 플로우 관리 네트워크 프로세서 구현)

  • Doo, Kyeong-Hwan;Lee, Bhum-Cheol;Kim, Whan-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37B no.9
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    • pp.814-821
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    • 2012
  • We propose a network processor called an OmniFlow processor capable of wire-speed flow management by a hardware-based flow admission control(FAC) in this paper. Because the OmniFlow processor can set up and release a wire-speed connection for flows, the update period of flows can be set to a short time, and only active flows can be effectively managed by terminating a flow that does not have a packet transmitted within this period. Therefore, the FAC can be used to provide a reliable transmission of UDP as well as TCP applications. This processor is fabricated in 65nm CMOS technology, and total gate count is 25 million. It has 40 Gb/s throughput performance in using the 32 RISC cores when maximum operating frequency is 555MHz.

Design and Performance Analysis of a Parallel Optimal Branch-and-Bound Algorithm for MIN-based Multiprocessors (MIN-based 다중 처리 시스템을 위한 효율적인 병렬 Branch-and-Bound 알고리즘 설계 및 성능 분석)

  • Yang, Myung-Kook
    • Journal of IKEEE
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    • v.1 no.1 s.1
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    • pp.31-46
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    • 1997
  • In this paper, a parallel Optimal Best-First search Branch-and-Bound(B&B) algorithm(pobs) is designed and evaluated for MIN-based multiprocessor systems. The proposed algorithm decomposes a problem into G subproblems, where each subproblem is processed on a group of P processors. Each processor group uses tile sub-Global Best-First search technique to find a local solution. The local solutions are broadcasted through the network to compute the global solution. This broadcast provides not only the comparison of G local solutions but also the load balancing among the processor groups. A performance analysis is then conducted to estimate the speed-up of the proposed parallel B&B algorithm. The analytical model is developed based on the probabilistic properties of the B&B algorithm. It considers both the computation time and communication overheads to evaluate the realistic performance of the algorithm under the parallel processing environment. In order to validate the proposed evaluation model, the simulation of the parallel B&B algorithm on a MIN-based system is carried out at the same time. The results from both analysis and simulation match closely. It is also shown that the proposed Optimal Best-First search B&B algorithm performs better than other reported schemes with its various advantageous features such as: less subproblem evaluations, prefer load balancing, and limited scope of remote communication.

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Implementation of a Simulation Tool for Monitoring Runtime Thermal Behavior (실시간 온도 감시를 위한 시뮬레이션 도구의 구현)

  • Choi, Jin-Hang;Lee, Jong-Sung;Kong, Joon-Ho;Chung, Sung-Woo
    • Journal of the Korea Society of Computer and Information
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    • v.14 no.1
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    • pp.145-151
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    • 2009
  • There are excessively hot units of a microprocessor in today's nano-scale process technology, which are called hotspots. Hotspots' heat dissipation is not perfectly conquered by mechanical cooling techniques such as heatsink, heat spreader, and fans; Hence, an architecture-level temperature simulation of microprocessors is evident experiment so that designers can make reliable chips in high temperature environments. However, conventional thermal simulators cannot be used in temperature evaluation of real machine, since they are too slow, or too coarse-grained to estimate overall system models. This paper proposes methodology of monitoring accurate runtime temperature with Hotspot[4], and introduces its implementation. With this tool, it is available to track runtime thermal behavior of a microprocessor at architecture-level. Therefore, Dynamic Thermal Management such as Dynamic Voltage and Frequency Scaling technique can be verified in the real system.

Implementation of a Sequence Controller for a Rocket Fire Control System through Processor-Hot Backup System (프로세서 이중화를 통한 로켓 발사통제시스템 시퀀스 컨트롤러 구현)

  • 문경록;김재문
    • Proceedings of the IEEK Conference
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    • 2003.07c
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    • pp.2795-2798
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    • 2003
  • 본 논문에서는 국내에서 개발하고 있는 과학로켓용 발사통제시스템(FCS, Fire Control System)의 시퀀스제어의 처리 영역을 PLC 시스템을 사용하여 구현하였다. 프로세서의 이중화를 통하여 Hot Backup 시스템을 구축하고 ControlNet 네트워크[l][2]를 기반으로 하는 프로세서와 I/O 간의 통신을 이용하였다. 먼저 로켓 발사통제시스템의 개요 및 주요 임무에 대하여 설명하고 기존에 사용된 발사통제시스템 구성을 분석하였다. PLC 시스템의 개요와 CPU 동작 내용 그리고 ControlNet 통신방식에 대하여 설명하고 프로세서를 이중화한 시스템을 제안하였다. 또한 이중화된 프로세서의 Switchover[2]방법을 알아보고 이러한 조건에 따른 PLC 시스템을 응용한 발사 통제시스템을 구성하여 이를 위해 작성된 시스템 운용 Ladder Diagram 프로그램에 대한 기술을 논하였다. 개발된 PLC 시스템의 구성을 제시하고 발사체 및 각종 지원시설과 연계한 시험을 통하여 성능을 검증하였다.

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