• Title/Summary/Keyword: 펄스폭 펄스주파수 변조기

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The power regulation of a High-Frequency Induction Heating System using Neuro-Fuzzy controller (뉴로퍼지제어기를 이용한 고주파 유도가열기의 정전력제어)

  • 장종승;설재훈;박종오;임영도;최부귀
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 1997.10a
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    • pp.41-44
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    • 1997
  • 본 논문에서는 뉴로퍼지제어기를 이용한 유도가열기의 시변부하에 대한 적응 정전력 제어를 하고자 한다. 유도가열기의 정전력 조절을 위해 IGBT를 사용한 위상전이형 펄스폭변조(PWM)와 PLL에 의한 부하공진주파수 추종형 펄스 주파수변수(PFM)가 조절되는 공진 고주파 인버터를 유용한 유도가열기를 설명하고, 실험 제작된 유도가열기에서의 부하에 대한 규정 전력 추종이 잘되고 있음이 실제적으로 논증되어졌다.

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Growth characteristic of lettuce (Lactuca sativa L.) based on Pulse Width modulation of artificial light sources with UV-A. (UV광원을 포함한 인공광원의 펄스폭 변조에 따른 적치마 상추의 생육특성)

  • Kwak, Su-Ji;Kwak, Eun-Ji;Lee, Hyun-Hee;Lee, Seung-Ki;Han, Jae-Woong;Jeon, Myung-Jin;Kim, Woong
    • Proceedings of the Korean Society for Agricultural Machinery Conference
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    • 2017.04a
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    • pp.123-123
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    • 2017
  • 식물공장 내 작물의 생육은 제공되는 인공광원의 광원 및 광질에 영향을 받으며, 광흡수 파장에 따라 다르다. 또한 광합성에 효과적인 형태의 빛의 계속적인 빛의 조사보다는 광 펄스를 조절하여 공급하여 준다면 더욱더 효과적인 생육 환경을 제공해 줄 수 있다. 식물의 최적 생장을 위해 특정 파장대의 빛을 선택적으로 조사할 수 있는 LED특성을 사용하여 UV광원을 포함한 인공광원의 펄스폭 변조에 따른 적치마 상추의 생육특성을 알아보고자 하였다. 광환경은 Red(660 nm), Blue(450 nm), UV(395 nm) LED를 8:1:1 비율로 광량 $160{\mu}mol{\cdot}m^2{\cdot}s^{-1}$, 주파수 1.25, 2.5, 3.75, 5.0 kHz로 조사하여 주었으며, 온도 $20{\sim}23^{\circ}C$, 습도 50~60%, $CO_2$농도 1,000 ppm으로 조성하여 주었다. 아시아종묘 적치마상추를 파종 후 18일 째 되는날 정식, 정식 후 14일 28일 째 되는날 SPAD, 지상부 지하부의 생체중 및 건물중, 엽폭, 엽장을 측정하였으며, 측정한 엽폭과 엽장을 이용하여 엽형지수 산출, 지상부 지하부 생체중 값을 이용하여 S/R율을 산출하였다. SPAD 측정결과 생육시기가 증가할수록 SPAD함량은 감소하였으며, 1.25와 2.5 kHz에서 생육 시기 증가에 대한 SPAD함량 감소가 컸고, 3.75와 5.0 kHz의 경우 SPAD함량의 감소량은 작았다. 지상부 생체중은 3.75 kHz에서 121.51 g으로 가장 높은 값을 나타냈으며, 2.5, 1.75, 5.0 kHz 순으로 높은 값을 나타났다. 지하부 생체중의 경우 3.75 kHz에서 31.31 g으로 가장 높은 값을 나타냈으며 2.5, 5.0, 1.25 kHz 순으로 높게 나타났다. 엽형지수는 생육 시기가 증가에 따라 감소하는 것으로 나타났으며, 1.75, 2.5, 5.0, 3.75 kHz 순으로 크게 나타났다. 지상부 건물중 측정결과는 지상부 생체중 결과와, 지하부 건물중의 측정결과는 지하부 생체중 결과와 동일하였다. S/R율은 1.75 kHz를 제외하고 생육시기가 증가할수록 S/R율은 감소하는 것으로 나타났으며, 주파수가 높아질수록 S/R율은 감소하는 것으로 나타났다. 엽형지수는 엽폭/엽장으로 엽형지수를 산출한 결과로 값이 작을수록 엽폭이 넓은 형태를 의미하며, 생체중값이 가장 크게 나타났던 3.75 kHz에서 엽형지수의 값이 가장 낮게 나타났으며 3.75 kHz를 제외하고 주파수가 높을수록 엽형지수의 값이 낮게 나타났다. 이에 주파수에 따른 적상추의 생육은 3.75 kHz에서 가장 좋은 것으로 판단할 수 있었다.

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Dynamic Modeling and Design of Controller based on Thrusters for Korean Lunar Module (달 착륙선의 동역학 모델링 및 추력기 기반 제어기 설계)

  • Yang, Sung-Wook;Lee, Sang-Chul
    • Journal of the Korean Society for Aviation and Aeronautics
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    • v.23 no.1
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    • pp.49-55
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    • 2015
  • This paper deals with dynamic modeling and controller design of a future Korean lunar module planned to be launched 2020's in Korea. For dynamic modeling of the lunar module, we first assume the lunar module as a rigid body. And we derive equations of motion for the lunar module by considering allocation of main thrusters and reaction thrusters. With the equation of motion, we design the controller based on the quaternion. A Pulse Width Pulse Frequency modulator(PWPFM) is selected for generating on/off signal. Finally, we construct a 2-phase descent mode including initial guidance mode, terminal guidance mode. The MATLAB simulation is performed for evaluating the descent ability and final landing velocity. The dynamic modeling and descent simulation of the lunar module in this paper could be applied for developing the future work of the Korean lunar exploration program.

A CMOS Band-Pass Delta Sigma Modulator and Power Amplifier for Class-S Amplifier Applications (S급 전력 증폭기 응용을 위한 CMOS 대역 통과델타 시그마 변조기 및 전력증폭기)

  • Lee, Yong-Hwan;Kim, Min-Woo;Kim, Chang-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.40 no.1
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    • pp.9-15
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    • 2015
  • A CMOS band-pass delta-sigma modulator(BPDSM) and cascode class-E power amplifier have been developed CMOS for Class-S power amplifier applications. The BPDSM is operating at 1-GHz sampling frequency, which converts a 250-MHz sinusoidal signal to a pulse-width modulated digital signal without the quantization noise. The BPDSM shows a 25-dB SQNR(Signal to Quantization Noise Ratio) and consumes a power of 24 mW at an 1.2-V supply voltage. The class-E power amplifier exhibits an 18.1 dBm of the maximum output power with a 25% drain efficiency at a 3.3-V supply voltage. The BPDSM and class-E PA were fabricated in the Dongbu's 110-nm CMOS process.

A Study on the Synthetic Aperture Radar Processor using AOD/CCD (AOD/CCD를 이용한 합성개구면 레이다 처리기에 관한 연구)

  • 박기환;이영훈;이영국;은재정;박한규
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.10
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    • pp.1957-1964
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    • 1994
  • In this thesis, a Synthetic Aperture Rarar Processor that is possible real-time handling is implemented using CW(Continuose Wave) laser as a light source, CCD(charge Coupled Device) as a time integrator, and AOD(Acousto-Optic Device) as the space integrator. One of the advantages of the proposed system is that it does not require driving circuits of the light source. To implement the system, the linear frequency modulation(chirp) technique has been used for radar signal. The received data for the unit target was processed using 7.80 board and accompanying electronic circuits. In order to reduce the smear effect of the focused chirp signal which occurs Bragg diffrection angle of the AOD has been utilized to make sharp pulses of the laser source, and the pulse made synchronized with the chirp signal. Experiment and analysis results of the data and images detected from CCD of the proposed SAR system demonstrated that detection effect is degrated as the unit target distance increases, and the resolving power is improved as the bandwidth of the chirp signal increases. Also, as the pulse width of the light source decreases, the smear effect has been reduced. The experimental results assured that the proposed system in this papre can be used as a real time SAR processor.

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Single-Stage APWM Half-Bridge Flyback Converter with Synchronous Rectifier (단일단 동기정류기형 APWM 하프브리지 플라이백 컨버터)

  • Park, Hae-Yong;Lee, Han-Mo;Kwon, Bong-Hwan
    • Proceedings of the KIPE Conference
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    • 2011.07a
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    • pp.360-361
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    • 2011
  • 본 논문에서는 단위역률과 고효율을 갖기 위한 단일단 동기정류기형 비대칭 하프브리지 플라이백 컨버터 회로를 제안한다. 제안된 회로에서는 역률 개선단을 통해 입력전류의 리플이 줄어들게 되며, 거의 단위역률에 가까운 고역률을 갖게 된다. 또한 비대칭 펄스폭 변조에 의한 하프브리지 플라이백 DC/DC 컨버터는 영전압 스위칭 (ZVS) 동작을 하게 되며, 출력단에 동기정류기를 사용하여 스위칭에 의한 손실을 줄였다. 출력전압 24V, 최대 출력 200W, 스위칭 주파수 100kHz에서 제안된 컨버터의 성능을 입증하기위해 실험이 진행 되었다.

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Design of a DC-DC Step-Down Converter for LED Backlight of Mobile Devices (휴대기기용 LED 백라이트를 위한 감압형 DC-DC 변환기 설계)

  • Son, Hyun-Sik;Lee, Min-Ji;Park, Won-Kyoung;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.15 no.3
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    • pp.1700-1706
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    • 2014
  • In this paper, a step down converter for LED backlight of mobile application has been proposed. The converter which is operated with 4 MHz high switching frequency is capable of reducing mounting area of passive devices consists of a power stage and a control block. Circuit elements of the power stage are inductor, output capacitor, MOS transistors and feedback resistors. The control block consists of pulse width modulator, error amplifier and oscillator etc. Proposed step down converter has been designed and verified using a $0.35{\mu}m$ 1-poly 4-metal BCD process technology. Simulation results show that the output voltage is 1.8 V in 3.7 V input voltage, output current 100 mA which is larger than 25 ~ 50 mA in conventional 500 KHz driven converter when the duty ratio is 0.4.

Design of a High-Efficiency CMOS DC-DC Boost Converter Using a Current-Sensing Feedback Method (전류 감지 Feedback 기법을 사용한 고효율 CMOS DC-DC Boost 변환기의 설계)

  • Jung Kyung-Soo;Yang Hui-Kwan;Cha Sang-Hyun;Lim Jin-Up;Choi Joong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.9 s.351
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    • pp.23-30
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    • 2006
  • This paper presents a design of a high-efficiency CMOS DC-DC boost converter using a current-sensing feedback method. High-precision current-sensing circuity is incorporated in order to sense the current flowing in the inductor, which determines the switching scheme of the pulse-width modulation. The external components or large chip area for the frequency compensation can be avoided while maintaining the stable operations of the converter. Various input/output voltage levels can be available through the external resistor strings. The designed DC-DC converter is fabricated in a 0.18-um CMOS technology with a thick-gate oxide option. The converter shows the maximum efficiency over 90% for the output voltage of 3.3V and load current larger than 200mA. The load regulation is 1.15% for the load current change of 100mA.

Development of High Voltage Generator for Diagnostic X-ray Equipment (진단용 X선 기기의 고전압 발생장치 개발)

  • Kim, Young-Pyo;Kim, Tae-Gon;Cheon, Min-Woo;Park, Yong-Pil
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.10a
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    • pp.764-765
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    • 2010
  • The medical treatment X-ray machineries used in diagnosis of the human body is possible to diagnosis inside of the human body with the method of noninvasive so that it has shared a very important role in diagnosis from the medical institution. High voltage occurrence system which is most important in occurrence of X-ray has mainly been used the existing type of high voltage transformer, however it has a low efficiency of X-ray occurrence since it is a big and heavy, and a high ripple ratio of the direct current high voltage come to the X-ray tube. In order to solve this problem, the research has been advanced about the high voltage power supply system, and the inverter type of the high voltage occurrence system which occurs a high voltage by increasing the power frequency from about ten times to about hundred times with the inverter has currently used mainly. Also, the operation of tube voltage and tube current was controlled by using PWM method and the operation results were identified using an oscilloscope.

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A study on the design exploration of Optical Image Stabilization (OIS) for Smart phone (스마트폰을 위한 광학식 손떨림 보정 설계 탐색에 관한 연구)

  • Lee, Seung-Kwon;Kong, Jin-Hyeung
    • Journal of Digital Contents Society
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    • v.19 no.8
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    • pp.1603-1615
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    • 2018
  • In order to achieve the low complexity and area, power in the design of Optical Image Stabilization (OIS) suitable for the smart phone, this paper presents the following design explorations, such as; optimization of gyroscope sampling rate, simple and accurate gyroscope filters, and reduced operating frequency of motion compensation, optimized bit width in ADC and DAC, evaluation of noise effects due to PWM driving. In experiments of gyroscope sampling frequencies, it is found that error values are unvaried in the frequency above 5KHz. The gyroscope filter is efficiently designed by combining the Fuzzy algorithm, to illustrate the reasonable compensation for the angle and phase errors. Further, in the PWM design, the power consumption of 2MHz driving is shown to decrease up to 50% with respect to the linear driving, and the imaging noises are reduced in the driving frequency above 2MHz driving frequency. The operating frequency could be reduced to 5KHz in controller and 10KHz in driver, respectively, in the motion compensation. For ADC and DAC, the optimized exploration experiments verify the minimum bit width of 11bits in ADC as well as 10bits in DAC without the performance degradation.