• Title/Summary/Keyword: 팬아웃

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A Main Memory-resident Multi-dimensional Index Structure Employing Partial-key and Compression Schemes (부분키 기법과 압축 기법을 혼용한 주기억장치 상주형 다차원 색인 구조)

  • 심정민;민영수;송석일;유재수
    • Journal of KIISE:Databases
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    • v.31 no.4
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    • pp.384-394
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    • 2004
  • Recently, to relieve the performance degradation caused by the bottleneck between CPU and main memory, cache conscious multi-dimensional index structures have been proposed. The ultimate goal of them is to reduce the space for entries so as to widen index trees and minimize the number of cache misses. The existing index structures can be classified into two approaches according to their entry reduction methods. One approach is to compress MBR keys by quantizing coordinate values to the fixed number of bits. The other approach is to store only the sides of minimum bounding regions (MBRs) that are different from their parents partially. In this paper, we propose a new index structure that exploits the properties of the both techniques. Then, we investigate the existing multi-dimensional index structures for main memory database system through experiments under the various work loads. We perform various experiments to show that our approach outperforms others.

lpCSB+- tree : An Enhanced Main Memory Index Structure Employing the Level Prefetching Technique (lpCSB+-트리 : 레벨 프리페칭 기법을 이용하는 향상된 주기억장치 상주형 색인구조)

  • Hong Hyun Taek;Pee Jun Il;Song Seok Il;Yoo Jae Soo
    • Journal of KIISE:Databases
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    • v.31 no.6
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    • pp.675-683
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    • 2004
  • In main-memory resident index structures, secondary cache misses considerably have an effect on the performance of index structures. Recently, several main-memory resident index structures that consider cache have been proposed to reduce the impact of secondary cache misses. However they still suffer from full secondary cache misses whenever visiting each level of a index tree. In this paper, we propose a new index structure that eliminates cache misses even when visiting each level of index tree. The proposed index structure prefetches the grandchildren of a current node. The basic structure of the proposed index structure is from CSB+-tree that uses the concepts of the node group to increase fan-out. However the insert algorithm of the proposed index structure reduces the cost of a split significantly. Also, we show the superiority of our algorithm through various performance evaluation.

Virtual Cell based $B^+$-tree Index Structure of Moving Objects for Location Based Services (위치 기반 서비스를 위한 가상 셀 기반 $B^+$-tree 이동객체 색인 기법)

  • Park, Yong-Hun;Seo, Dong-Min;Song, Seok-Il;Yoo, Jae-Soo
    • Proceedings of the Korean Information Science Society Conference
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    • 2010.06c
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    • pp.185-190
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    • 2010
  • 최근 위치 인식 기술과 휴대 장치의 발달로 인해 이동하는 객체를 기반으로 하는 위치 기반 서비스(Location Based Service, LBS)의 관심이 점점 증가하고 있고 그에 관련된 연구들이 활발하게 진행되고 있다. 이동 객체의 응용은 빈번하게 변경되는 이동객체의 위치정보를 효과적으로 처리할 수 있는 색인구조를 필요로 한다. 위치정보를 색인하기 위해 R-tree 기반의 색인들이 제안되었다. 하지만 R-tree는 변경보다는 검색 연산에 초점이 맞추어진 색인구조이기 때문에 잦은 변경을 다루어야 하는 이동객체 환경에 적합하지 못하다. 최근 이러한 객체의 빠른 위치 변경을 지원하는 그리드 기반의 색인 구조가 제안되었다. 하지만 셀의 객체 점유율에 따라 검색 속도가 저하되는 단점은 여전히 해결되지 못하고 있다. 이러한 단점은 객체들이 특정 영역에 몰리는 경우 또는 그리드의 해상도를 잘못 지정한 경우 더욱 부각된다. 본 논문에서는 이러한 단점을 해결하기 위해 가상 셀 기반의 색인 구조를 제안한다. 데이터 페이지에 객체의 점유율을 보장하기 위해 여러 개의 인접한 셀들의 데이터를 한 데이터 페이지에 함께 저장한다. 공간 채움 곡선을 기반으로 순서화된 셀들로 셀의 인접성을 결정한다. 또한 공간 채움 곡선의 차수를 동적으로 지정하여 객체가 집중된 셀에 대해서는 셀의 단위 크기를 작게 지정한다. 뿐만 아니라 셀을 표현하기 위한 식별자를 위해 비트를 이용한 표현식을 제안하였다. 이로 인해 노드의 팬아웃을 증가시켰고, 저장공간을 절약하였다. 실험을 통해서 제안하는 색인 기법의 우수성을 증명하였다.

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Analysis of Warpage of Fan-out Wafer Level Package According to Molding Process Thickness (몰드 두께에 의한 팬 아웃 웨이퍼 레벨 패키지의 Warpage 분석)

  • Seung Jun Moon;Jae Kyung Kim;Euy Sik Jeon
    • Journal of the Semiconductor & Display Technology
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    • v.22 no.4
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    • pp.124-130
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    • 2023
  • Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

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Development of CPLD Technology Mapping Algorithm for Sequential Circuit Improved Run-Time Under Time Constraint (시간제약 조건하에서 순차 회로를 위한 수행시간을 개선한 CPLD 기술 매핑 알고리즘 개발)

  • Yun, Chung-Mo;Kim, Hui-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.4
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    • pp.80-89
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    • 2000
  • In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the$^1$costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that it fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs by 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

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An Efficient CPLD Technology Mapping considering Area under Time Constraint (시간 제약 조건하에서 면적을 고려한 효율적인 CPLD 기술 매핑)

  • Kim, Jae-Jin;Kim, Hui-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.1
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    • pp.79-85
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    • 2001
  • In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.

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Effects of Dielectric Curing Temperature and T/H Treatment on the Interfacial Adhesion Energies of Ti/PBO for Cu RDL Applications of FOWLP (FOWLP Cu 재배선 적용을 위한 절연층 경화 온도 및 고온/고습 처리가 Ti/PBO 계면접착에너지에 미치는 영향)

  • Kirak Son;Gahui Kim;Young-Bae Park
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.2
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    • pp.52-59
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    • 2023
  • The effects of dielectric curing temperature and temperature/humidity treatment conditions on the interfacial adhesion energies between Ti diffusion barrier/polybenzoxazole (PBO) dielectric layers were systematically investigated for Cu redistribution layer applications of fan-out wafer level package. The initial interfacial adhesion energies were 16.63, 25.95, 16.58 J/m2 for PBO curing temperatures at 175, 200, and 225 ℃, respectively. X-ray photoelectron spectroscopy analysis showed that there exists a good correlation between the interfacial adhesion energy and the C-O peak area fractions at PBO delaminated surfaces. And the interfacial adhesion energies of samples cured at 200 ℃ decreased to 3.99 J/m2 after 500 h at 85 ℃/85 % relative humidity, possibly due to the weak boundary layer formation inside PBO near Ti/PBO interface.