• Title/Summary/Keyword: 패스 설계

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Indoor Positioning Using RFID Technique (RFID 기술을 이용한 실내 위치 추적)

  • Yoon, Chang-sun;Kim, Tae-in;Kim, Hyeon-jin;Hong, Yeon-chan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.1
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    • pp.207-214
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    • 2016
  • RFID technology is a technology perceiving information with the device called reader and tag which is now used in public transportation such as Hi-pass. In this paper, we design a system which tracks indoor location using this technology. GPS, the most frequently used location-tracking system, has a defect that its accuracy decreases when the device is indoor. In suggested experiment, we simulate signals according to the moving of located objects, then compare with the result of the experiment. Based on the extracted data, we inform data which is for the purpose of tracking system based on analysis of the route and errors. Simulations for the tracking were performed with relocation of real objects. In the real experiment, we arrange the readers around the room and move the tagged object that we like to know the location, then analyze the data from the equipment. This paper suggests the analyzed data for the future indoor tag tracking applications. We expect that the RFID based location positioning data will be used for other indoor positioning research and development.

VLSI Design of DWT-based Image Processor for Real-Time Image Compression and Reconstruction System (실시간 영상압축과 복원시스템을 위한 DWT기반의 영상처리 프로세서의 VLSI 설계)

  • Seo, Young-Ho;Kim, Dong-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.1C
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    • pp.102-110
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    • 2004
  • In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

Low-Cost Elliptic Curve Cryptography Processor Based On Multi-Segment Multiplication (멀티 세그먼트 곱셈 기반 저비용 타원곡선 암호 프로세서)

  • LEE Dong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.8 s.338
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    • pp.15-26
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    • 2005
  • In this paper, we propose an efficient $GF(2^m)$ multi-segment multiplier architecture and study its application to elliptic curve cryptography processors. The multi-segment based ECC datapath has a very small combinational multiplier to compute partial products, most of its internal data buses are word-sized, and it has only a single m bit multiplexer and a single m bit register. Hence, the resource requirements of the proposed ECC datapath can be minimized as the segment number increases and word-size is decreased. Hence, as compared to the ECC processor based on digit-serial multiplication, the proposed ECC datapath is more efficient in resource usage. The resource requirement of ECC Processor implementation depends not only on the number of basic hardware components but also on the complexity of interconnection among them. To show the realistic area efficiency of proposed ECC processors, we implemented both the ECC processors based on the proposed multi-segment multiplication and digit serial multiplication and compared their FPGA resource usages. The experimental results show that the Proposed multi-segment multiplication method allows to implement ECC coprocessors, requiring about half of FPGA resources as compared to digit serial multiplication.

NCS-based Education & Training and Qualification Proposal for Work-Learning Parallel Companies Introducing Smart Manufacturing Technology (스마트 제조기술을 도입하는 일학습병행 학습기업을 위한 NCS 기반 교육훈련 및 자격 제안)

  • Choi, Hwan Young
    • Journal of Practical Engineering Education
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    • v.12 no.1
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    • pp.117-125
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    • 2020
  • According to the government's smart factory promotion project for small and medium-sized enterprises, more than 10,000 intelligent factories are scheduled or already built in the country and the government-led goal is to nurture 100,000 skilled workers by 2022. Smart Factory introduces numerous types of education and training courses from the supplier's point of view, such as training institutions belonging to local governments, some universities, and public organizations, in the form of an efficient resource management system and ICT technology convergence in the automated manufacturing equipment. The lack of linkage with the NCS, the standard for training, seems to have room for rethinking and direction. Results of survey is provided for the family companies of K-University in the metropolitan area and Chungnam area, and analyzes job demands by identifying whether or not they want to introduce smart factories. Defining the practitioners who will serve as a window for the introduction of smart factory technology within the company, setting up a training goal in consideration of the career path, and including the level of training required competency units, optional competency units, and training time suitable for introducing and operating smart factories. Author would like to present an NCS-based qualification design plan.

Seismic Performance of Concrete-Filled Steel Piers Part I : Quasi-Static Cyclic Loading Test (강합성교각의 내진성능평가 Part I : 준정적 반복재하실험)

  • 조창빈;서진환;장승필
    • Journal of the Earthquake Engineering Society of Korea
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    • v.6 no.2
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    • pp.9-19
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    • 2002
  • Steel piers and concrete-filled steel(CFS) piers, in spite of reasonable strength, high ductility, small section, and fast construction, have not been considered as one of alternatives to RC piers even in the highly populated urban area where aseismic safety, limited space and fast construction are indispensably required. This paper, the first of two companion papers for the seismic performance of steel and CFS piers, tests steel and CFS piers under quasi-static cyclic loading to estimate their ductility and strength. Additional details such as rebars and base ribs are added to increase the ductility of a concrete-filled steel pier with minimum additional cost. Also, simplified numerical analyses using nonlinear spring and shell elements are examined for the estimation of the ductility and strength of concrete-filled steel piers and a steel pier. The result shows that concrete-filled steel peirs have higher energy absorption, i.e., ductility and strength than those of steel pier and increasing bonding between in-filled concrete and lower diaphragm, and the improved details of stress concentrated region would be important for the ductility and strength of a pier. Numerical results show that simplified modeling with nonlinear springs and shells has potential to be effective modeling technique to estimate the seismic performance of a concrete-filled steel pier.

A Mobile Application Model for Local and Tour Information Services (향토관광정보서비스를 위한 모바일 앱 모형)

  • Yi, Yong Jeong;Yi, Dajeong;Lee, Changho;Yoon, Sohyun
    • Journal of the Korean Society for information Management
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    • v.36 no.1
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    • pp.247-267
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    • 2019
  • There has been low use of local information services that public libraries provide, and most of those services are limited only through in-house reading or checkout. Motivated by these issues, the study has developed a mobile application (app, hereafter) entitled as LibPass (a combination of Library and Pass) to propose new local information services that reflect the information needs of users. Regarding the design of LibPass, contents of LibPass are composed of the characteristics of local resources so that users can easily search for information about local culture and tour resources through mobile app. That is, it aims to provide efficient information services on local resources by providing information on accommodations, outdoor programs, and specialized libraries, as well as introducing tour resources. Above all, the services are provided with a single card issued by the National Library of Korea and is convenient to use anywhere in the country. It not only secures reliability and currency by utilizing various contents developed by public institutions, but also provides functions to facilitate specialized services for the local information of libraries. Based on the previous research, the present study derives the factors of quality evaluation of mobile tour information services; it constructs objects of LibPass application by analyzing existing applications and develops the prototype based on logical entity relationship model. This model can contribute to the increased use of local information services and, promotes the public's positive perception of the libraries through user-friendly applications.

Unsupervised Non-rigid Registration Network for 3D Brain MR images (3차원 뇌 자기공명 영상의 비지도 학습 기반 비강체 정합 네트워크)

  • Oh, Donggeon;Kim, Bohyoung;Lee, Jeongjin;Shin, Yeong-Gil
    • The Journal of Korean Institute of Next Generation Computing
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    • v.15 no.5
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    • pp.64-74
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    • 2019
  • Although a non-rigid registration has high demands in clinical practice, it has a high computational complexity and it is very difficult for ensuring the accuracy and robustness of registration. This study proposes a method of applying a non-rigid registration to 3D magnetic resonance images of brain in an unsupervised learning environment by using a deep-learning network. A feature vector between two images is produced through the network by receiving both images from two different patients as inputs and it transforms the target image to match the source image by creating a displacement vector field. The network is designed based on a U-Net shape so that feature vectors that consider all global and local differences between two images can be constructed when performing the registration. As a regularization term is added to a loss function, a transformation result similar to that of a real brain movement can be obtained after the application of trilinear interpolation. This method enables a non-rigid registration with a single-pass deformation by only receiving two arbitrary images as inputs through an unsupervised learning. Therefore, it can perform faster than other non-learning-based registration methods that require iterative optimization processes. Our experiment was performed with 3D magnetic resonance images of 50 human brains, and the measurement result of the dice similarity coefficient confirmed an approximately 16% similarity improvement by using our method after the registration. It also showed a similar performance compared with the non-learning-based method, with about 10,000 times speed increase. The proposed method can be used for non-rigid registration of various kinds of medical image data.

A Study on the Evaluation the Safety of Evacuation in Indoor Sports Stadium through Evacuation Simulation (피난시뮬레이션을 통한 실내 스포츠경기장 내 장애인의 피난 안전성 평가 연구)

  • MinEon Ju;SeHong Min
    • Journal of the Society of Disaster Information
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    • v.20 no.1
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    • pp.69-81
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    • 2024
  • Purpose: Recently, there has been a movement to guarantee the right to watch sports for the disabled. However, the sports stadium is designed without considering the wheelchair users, so the right to move in the stadium is not secured. Restrictions on the movement of the disabled make the evacuation vulnerable in an emergency. This study aims to develop a plan to ensure the safety of movement and evacuation of wheelchair users by conducting simulations targeting indoor sports stadiums. Method: The simulation was performed by constructing a scenario with the shape of the stands as a variable. The effect of the installation of wheelchair seats on evacuation was confirmed. Result: The results according to whether wheelchair seats are installed, the evacuation route of wheelchair movement, and whether wheelchair seats are separately arranged were compared. The impact of wheelchair seat installation on evacuation and its characteristics were derived. As a result, upward and separation seat was the most vulnerable to evacuation. Conclusion: A plan to secure evacuation performance was derived for the top floors of upward and separation seat. It is judged that the content can be use as a way to secure the safety of movement and evacuation of the disabled in sports stadiums.

Hybrid Scheme of Data Cache Design for Reducing Energy Consumption in High Performance Embedded Processor (고성능 내장형 프로세서의 에너지 소비 감소를 위한 데이타 캐쉬 통합 설계 방법)

  • Shim, Sung-Hoon;Kim, Cheol-Hong;Jhang, Seong-Tae;Jhon, Chu-Shik
    • Journal of KIISE:Computer Systems and Theory
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    • v.33 no.3
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    • pp.166-177
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    • 2006
  • The cache size tends to grow in the embedded processor as technology scales to smaller transistors and lower supply voltages. However, larger cache size demands more energy. Accordingly, the ratio of the cache energy consumption to the total processor energy is growing. Many cache energy schemes have been proposed for reducing the cache energy consumption. However, these previous schemes are concerned with one side for reducing the cache energy consumption, dynamic cache energy only, or static cache energy only. In this paper, we propose a hybrid scheme for reducing dynamic and static cache energy, simultaneously. for this hybrid scheme, we adopt two existing techniques to reduce static cache energy consumption, drowsy cache technique, and to reduce dynamic cache energy consumption, way-prediction technique. Additionally, we propose a early wake-up technique based on program counter to reduce penalty caused by applying drowsy cache technique. We focus on level 1 data cache. The hybrid scheme can reduce static and dynamic cache energy consumption simultaneously, furthermore our early wake-up scheme can reduce extra program execution cycles caused by applying the hybrid scheme.