• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• The Journal of the Acoustical Society of Korea
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• v.22 no.2
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• pp.135-144
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• 2003

A method for the automatic segmentation of speech signals is described. The method is dedicated to the construction of a large database for a Text-To-Speech (TTS) synthesis system. The main issue of the work involves the refinement of an initial estimation of phone boundaries which are provided by an alignment, based on a Hidden Market Model(HMM). Multi-layer perceptron (MLP) was used as a phone boundary detector. To increase the performance of segmentation, a technique which individually trains an MLP according to phonetic transition is proposed. The optimum partitioning of the entire phonetic transition space is constructed from the standpoint of minimizing the overall deviation from hand labelling positions. With single speaker stimuli, the experimental results showed that more than 95% of all phone boundaries have a boundary deviation from the reference position smaller than 20 ms, and the refinement of the boundaries reduces the root mean square error by about 25%.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.298-306
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• 2011

In this paper, the RUNCODE encoder hardware IP was designed and implemented for symbol ID code length encoding, which is one of major modules of JBIG2 encoder for FAX. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the hardware generation and synthesis of VHDL code. The synthesized hardware was downloaded to Virtex-4 FX60 FPGA on ML410 development board. The synthesized hardware utilizes 13% of total slice of FPGA. Using Active-HDL tool, the hardware was verified showing normal operation. Compared with the software operating using Microblaze cpu on ML410 board, the synthesized hardware was better in operation time. The improvement ratio of operation time between the synthesized hardware and software showed about 40 times faster than software only operation. The synthesized H/W and S/W module cooperated to succeed in compressing the CCITT standard document.

• Journal of KSNVE
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• v.1 no.1
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• pp.7-19
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• 1991

해사기술연구소가 보유하고 있는 6자유도 대형진동대의 시스템 구성과 시험파형 합성기법 및 시험방법에 대하여 간략히 살펴보았다. 통상적인 가진기가 1방향의 운동만을 구현할 수 있음에 비해, 6자유도 진동대는 3축병진, 3축 회전의 임의의 복잡운동을 구현할 수 있는 국내 유일의 설비이며 용량 또한 30톤의 시험체까지를 대상으로 한 대형 진동대로서 각종 분야에 필요한 진동시험 업무를 지원할 수 있다. 구조물의 방진 및 내진설계를 위해서는 가능한한 실물 또는 모형의 실증실험이 필수적이며, 이는 내진 해석기법의 개발 및 검증의 기초가 된다. 특히 이 시스템은 내진 검증시험에 필요한 모든 기능을 갖추고 있으므로, 앞으로 건설될 국내원자력 발전소에 이용되는 각종기기의 내진검증시험을 통하여 이들 기기의 국산화에 크게 이바지할 것으로 보인다.

• Transactions of the Korean Society of Mechanical Engineers
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• v.15 no.5
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• pp.1683-1696
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• 1991

본 연구에서는 정4각단면덕트 입구영역에서 층류맥동유동(laminar pulsating flows)의 유동특성을 이론 및 실험적으로 규명하기 위하여, 이론적 방법으로 덕트 입 구영역에서의 층류맥동유동에 대한 운동량방정식을 유도한 후 비선형인 대류항을 선형 화 시켜서 라플라스변환으로 속도분포식의 해를 구하였고, 실험적인 방법으로는 시험 덕트 크기는 횡단면의 가로*세로가 40mm*40mm이고, 길이가 4000mm인 정4각단면덕트 입구영역에서 송풍기에 의한 공기흡입유동으로 층류진동유동을 발생하며 이들 두유동 을 합성시켜 발생한 층류맥동유동에 대하여 열선유속계의 열선신호로부터 얻어진 속도 파형을 고찰하여 덕트내의 맥동유동에 대한 임계레이놀즈수를 결정하고 속도분포를 측 정하였다. 그리고 이론적으로 얻어진 속도분포식과 열선유속계로 측정한 속도분포를 비교검토하여 정확성을 검증하고, 이들 해석결과로 부터 층류맥동유동의 입구길이(en- trance lenght)식을 결정하여 제안하였다.

• The Journal of Engineering Research
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• v.2 no.1
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• pp.147-149
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• 1997

Nirogen dioxide is rapidly converted to nitric oxide by the water absortbed on a Linde Molecular Sieve column. The resultant wave form is indistinguishable from that of pure nitric oxide introduced to the column. Thus, by conversion to the low boiling nitric oxide, the complication of oxidation of organic partitioning liquids is obviated.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.7
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• pp.17-26
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• 1999

In this paper, Bit selectable and Bi-directional Interface Device is described, which can communicate data with the peripheral devices. Specially, an algorithm of truth-table comparison that synthesizes the pulse-type sequential circuit pulse has been proposed to design the Interrupt Generator, and implemented in designing the Interrupt Register. Also, a description of the asynchronous design method is given to remove the clock skew phenomenon, and the output asynchronous control method which finds the optimal clock and controls all the enable signal of the output pins at the same time is presented. Using this technique interface ports have delay time of less-than 0.7ns.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.7 no.3
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• pp.27-33
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• 1993

This paper presents the &tal controller for driving high frequency voltage fed PWM inverter that carrier frequency is over 2OkHz.We analyzed the conventional PWM to select a proper PWM pattern. as the result, obtained PWM pattern of the controller in which asynchronus staircase sinusoidal waveform is used as reference signal, and variable carrier ratio method was used for PWM control. The PWM controller is designed by fully digital method. Especially, Thk proposed controller is consisted of 8 bit one-chip microprocessor and digital logic. the former is for arithmetic and data processing, and the latter is for PWM pattern synthesis. Therefore, The responsibility and controllability is improved. Also, Data processing capability is improved using proper program to output modulation index with 9 bits. Circuits configuration of digital controller are made up of one chip 8051 and EPLD, and its controllability is tested by operating voltage fed inverter. Harmonics and current waveform is evaluated and analyzed for the voltage fed inverter system.

• Journal of the Korean Institute of Intelligent Systems
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• v.17 no.7
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• pp.957-963
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• 2007

In this paper, Nonlinear Autoregressive (NAR) method based on Least Square-Support Vector Regression (LS-SVR) is introduced and tested for nonlinear sustained vowel modeling. In the database of total 43 sustained vowel of Benign Vocal Fold Lesions having aperiodic waveform, this nonlinear synthesizer near perfectly reproduced chaotic sustained vowels, and also conserved the naturalness of sound such as jitter, compared to Linear Predictive Coding does not keep these naturalness. However, the results of some phonation are quite different from the original sounds. These results are assumed that single-band model can not afford to control and decompose the high frequency components. Therefore multi-band model with wavelet filterbank is adopted for substituting single band model. As a results, multi-band model results in improved stability. Finally, nonlinear sustained vowel modeling using NAR based on LS-SVR can successfully reconstruct synthesized sounds nearly similar to original voiced sounds.