• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.345-352
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• 2017

In this paper, a unified potentiostat which can measure the current of both $O_2$-based and $H_2O_2$-based blood glucose sensors with low supply voltage of 1.0V has been designed and verified by simulations and measurements. Potentiostat is composed of low-voltage operational transconductance amplifier, cascode current mirrors and mode-selection circuits. It can measure currents of blood glucose chemical reactions occurred by $O_2$ or $H_2O_2$. The body of PMOS input differentional stage of the operational transconductance amplifier is forward-biased to reduce the threshold voltage for low supply voltage operation. Also, cascode current mirror is used to reduce current measurement error generated by channel length modulation effects. The proposed low-voltage potentiostat is designed and simulated using Cadence SPECTRE and fabricated in Magnachip 0.18um CMOS technology with chip size of $110{\mu}m{\times}60{\mu}m$. The measurement results show that consumption current is maximum $46{\mu}A$ at supply voltage of 1.0V. Using the persian potassium($K_3Fe(CN)_6$) equivalent to glucose, the operation of the fabricated potentiostat was confirmed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.