• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1167-1173
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• 2005

In this paper, the use of an antenna array is considered for code timing acquisition of DS-CDMA signals. The probabilities of acquisition are evaluated by applying multiple narrow fixed-beams to the conventional MUSIC acquisition approach in the multiuser environment on the time-varying Rayleigh fading channel. Each fixed-beam for spatial filtering is dedicated to an individual angular sector that is formed by dividing the entire angular domain by the number of antenna elements. The fixed-beams with a capability of interference suppression provide the additional degrees of freedom,. Hence, the multibeam-based MUSIC estimator can be used to synchronize to more users than the conventional MUSIC algorithm for one antenna. The multibeam-based subspace method is evaluated to significantly improve the performance of a single antenna based MUSIC technique in multiuser scenarios.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.7
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• pp.98-105
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• 2005

In this paper, the decryption function of CCSDS telecommand of CTU EQM for the security of communications satellite was verified. In order to intensify the security level of DES CFB decryption algorithm applied to CTU EM, 3DES CFB decryption algorithm using three keys is implemented in the CTU EQM. As the decryption keys increased due to the 3DES algorithm, the keys and IV are stored in PROM memory, and used for the telecommand decryption by taking the keys and IVs corresponding to the selected key and IV indexes from the memory. The operation of the 3DES CFB is validated through the timing simulation of 3DES CFB algorithm, and then the 3DES CFB core implemented on the A54SX32 FPGA. The test environment for the telecommand decryption verification of the CTU EQM was built up. Through sending and decrypting the encrypted command, monitoring the opcodes, and confirming LED on/off by executing the opcodes, the 3DES CFB telecommand decryption function of the CTU EQM is verified.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.1-6
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• 2020

This paper proposes the design of an advanced S-Box for calculating multiplicative inverse in AES encryption process. In this approach, advanced S-box module is first designed based on composite field, and then the performance evaluation is performed for S-box with multi-stage pipelining architecture. In the proposed S-Box architecture, each module for multiplicative inverse is constructed using combinational logic for realizing both small-area and high-speed. Through logic synthesis result, the designed 3-stage pipelined S-Box shows speed improvement of about 28% compared to the conventional method. The proposed advanced AES S-Box is performed modelling at the mixed level using Verilog-HDL, and logic synthesis is also performed on Spartan 3s1500l FPGA using Xilinx ISE 14.7 tool.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.12
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• pp.1412-1422
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• 2010

A bistatic radar using the pulse chasing can detect a target to track successive transmitted pulses using a receive beam for effectively scanning the cosite search area. When tracking a transmitted pulse with the receive beam, some beam pointing errors within pulse-to-pulse can cause the timing error in received pulse and the variation of the signal strength. In this paper, we have proposed that some errors due to the receive beam pointing error could limit the MTI filter's performance and derived that the relationship between the MTI performance and the geometric factors which are the inherent properties in bistatic configuration. Through the simulation, we have considered the limitations of the improvement performance restricted by the receiving beam pointing error and confirmed the contribution to the performance improvement in maintaining the receiving beam pointing error of under 0.5 degrees.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12C
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• pp.1193-1200
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• 2005

In this paper, we proposed an image hiding method which decreases the amount of calculation encrypting partial data rather than the whole image data using a discrete wavelet transform and a linear scalar quantization which have been adopted as the main technique in JPEG2000 standard and then implemented the proposed algorithm to hardware. A chaotic system was used instead of encryption algorithms to reduce further amount of calculation. It uses a method of random changing method using the chaotic system of the data in a selected subband. For ciphering the quantization index it uses a novel image encryption algorithm of cyclical shifting to the right or left direction and encrypts two quantization assignment method (Top-down coding and Reflection coding), made change of data less. The experiments have been performed with the proposed methods implemented in software for about 500 images. The hardware encryption system was synthesized to find the gate-level circuit with the Samsung $0.35{\mu}m$ Phantom-cell library and timing simulation was performed, which resulted in the stable operation in the frequency above 100MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.429-438
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• 2004

In this paper, a decision-feedback coherent code tracking loop is designed for WCDMA systems and its performance is analyzed in terms of jitter variance considering the effect of phase and symbol estimation errors for both AWGN and fading environments. An analytical closed-form formula for jitter variance is Int derived for AWGN environments as a function of a pulse-shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth while involving the phase estimation error and bit error rate, and the upper bound of jitter variance is derived for fading environments. Finally a second-order coherent code tracking loop is designed with the DPCH frame format #13 of the WCDHA forward link selected as a target system, and its performance is evaluated by the closed-form formula and compared with the simulation results for both AWGN and Rayleigh fading environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.2A
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• pp.159-166
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• 2008

In this paper, we proposed an algorithm to solve the problem that can't maintain hop synchronization using only early-late gate tracking loop due to the drift of geo-stationary satellite in frequency hopping satellite communication system. When the signal is transferred to downlink through DRT(Dehop-Rebop Transponder), the problem with synchronization loss is occurred periodically when using only early-late gate tracking loop, because of energy loss in each side portion of hop due to orbital variation of the satellite. To solve this problem, we have developed Anti-Shrink synchronization tracking algorithm which uses the prediction value of transmission timing and the structure of inner-outer gate instead of early-late gate with the ranging information. Through simulations, we showed that the performance of the Anti-Shrink algorithm is better than that of simple inner-outer energy ratio algorithm and similar to that of conventional early-late tracking loop algorithm with ranging information. No synchronization failure in the proposed algorithm was occurred because of less energy loss and robustness without the ranging information.

• Journal of Broadcast Engineering
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• v.10 no.3
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• pp.401-412
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• 2005

We propose and design the algorithms of symbol timing recovery, carrier recovery, and equalization for the receiver of S-DMT cable modem, which supports more channels and better symmetric mutimedia services over HFC network. We evaluate the performance of the concatenated entire receiving system of 16QAM, 64QAM in the mixed noise channel of AWGN, ISI and impulse. The result of evaluation shows those algorithms work correctly and designed S-DMT receiver has good performance. We also verify the designed system has excellent immunity against impulse noise channel of practical Cable TV networks by the result of simulation with the parameters of impulse internal $\varepsilon$ and noise power $\gamma^{k}$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2032-2038
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• 2007

Embedded Controller which controls whole system is most important part of embedded system. Nowadays, new technique called SoC is more using than ASIC. But SoC have some problems. Because of long development time and high cost, it is hard to applying SoC to small and medium enterprise. So many companies use IP technique combined with embedded processor. High resolution inkjet marking system is printing system with embedded controller. It is used in various part of industry. But it has many problems such as printing quality, marking errors, system faults and so on. In this paper, we designed and implemented IP that can solve the printing quality problems. We analyzed total-logic-elements and timing by simulation. As a result of simulation, we could verified that output signals satisfied reference timing. Appling IP to high resolution inkjet marking system, we could get good quality printing message.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.11
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• pp.271-276
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• 2019

Conventional ARIA algorithm which is used LUT based-S-Box is fast the processing speed. However, the algorithm is hard to applied to small portable devices. This paper proposes the hardware design of optimized ARIA crypto-processor based on the modified composite field S-Box in order to decrease its hardware area. The Key scheduling in ARIA algorithm, both diffusion and substitution layers are repeatedly used in each round function. In this approach, an advanced key scheduling method is also presented of which two functions are merged into only one function for reducing hardware overhead in scheduling process. The designed ARIA crypto-processor is described in Verilog-HDL, and then a logic synthesis is also performed by using Xilinx ISE 14.7 tool with target the Xilnx FPGA XC3S1500 device. In order to verify the function of the crypto-processor, both logic and timing simulation are also performed by using simulator called ModelSim 10.4a.