• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.42 no.2 s.302
• /
• pp.27-36
• /
• 2005

This thesis proposed an effective encryption method for the DCT-based image/video contents and made it possible to operate in a high speed by implementing it as an optimized hardware. By considering the increase in the amount of the calculation in the image/video compression, reconstruction and encryption, an partial encryption was performed, in which only the important information (DC and DPCM coefficients) were selected as the data to be encrypted. As the result, the encryption cost decreased when all the original image was encrypted. As the encryption algorithm one of the multi-mode AES, DES, or SEED can be used. The proposed encryption method was implemented in software to be experimented with TM-5 for about 1,000 test images. From the result, it was verified that to induce the original image from the encrypted one is not possible. At that situation, the decrease in compression ratio was only $1.6\%$. The hardware encryption system implemented in Verilog-HDL was synthesized to find the gate-level circuit in the SynopsysTM design compiler with the Hynix $0.25{\mu}m$ CMOS Phantom-cell library. Timing simulation was performed by Verilog-XL from CadenceTM, which resulted in the stable operation in the frequency above 100MHz. Accordingly, the proposed encryption method and the implemented hardware are expected to be effectively used as a good solution for the end-to-end security which is considered as one of the important problems.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.4
• /
• pp.659-666
• /
• 2006

Servo-motors are used as key components of automated system by performing precise motion control as accurate positioning and accurate speed regulation in response to the commands from computers and sensors. Especially, the linear brushless servo-motors have numerous advantages over the rotary servo motors which have connection with the friction induced transfer mechanism such as ball screws, timing belts, rack/pinion. This paper proposes an estimation method of unknown motor system parameters using the informations from the sinusoidal driving type linear brushless DC motor dynamics and outputs. The estimated parameters can be used to tune the controller gain and a disturbance observer. In order to meet this purpose high performance Digital Signal Processor, TMS320F240, designed originally for implementation of a Field Oriented Control(FOC) technology is adopted as a controller of the liner BLDC servo motor. Having A/D converters, PWM generators, rich I/O port internally, this servo motor application specific DSP play an important role in servo motor controller. This linear BLDC servo motor system also contains IPM(Intelligent Power Module) driver and hail sensor type current sensor module, photocoupler module for isolation of gate signals and fault signals.

• Korean Journal of Applied Biomechanics
• /
• v.19 no.1
• /
• pp.37-47
• /
• 2009

This study develops a technique training program to enhance the completion of Kolman, the high air flight technique, and applies it to two national athletes of the horizontal bar, one of the gymnastic events, for eight weeks. After that, their improvement was measured through 3D motion analysis to help them elevate their performance. The training program includes swing, hand release, twist, and bar hold, and its implementation produced the results stated below. They were made to practice the motion in the following way. After the hand-standing of giant swing which initiates the motion, they lift their body upward a little bit more. Next, they take their body down almost like a vertical descent and make a deep tap swing. Instead of doing the tap swing which widens the flection of hip and shoulder joints, while body revolution is more emphasized in particular, they release the bar as raising the centroid of their body sufficiently. During the flight, they try to narrow every joint in their body. As a result, the bar's elasticity becomes greatly increased, and since the backing rate of their body gets higher, the centripetal force of the swing is improved that they can release the bar in the higher position. In addition, because they can erect their body faster during the flight, they can perform comfortable twist and revolution in the air. They can also adjust the direction of the flight easily without too much concern for the proper timing of hand release as they rise. Thereby, they can not only maintain adequate distance from the bar for the bar hold but also ensure enough distance for body revolution and twist.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.7A
• /
• pp.683-694
• /
• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.5C
• /
• pp.527-539
• /
• 2009

In this paper, we propose an asynchonous ICI (Inter-Cell Interference) mitigation techniques for 3GPP LTE MIMO-OFDMA down-link receiver. An increasing in symbol timing misalignments may occur relative to sychronous network as the result of BS (Base Station) timing differences. Such symbol synchronization errors that exceed the guard interval or the cyclic prefix duration may result in MAI (Multiple Access Interference) for other carriers. In particular, at the cell boundary, this MAI becomes a critical factor, leading to degraded channel throughput and severe asynchronous ICI. Hence, many researchers have investigated the interference mitigation method in the presence of asynchronous ICI and it appears that the knowledge of the SCM (Spatial Covariance Matrix) of the asynchronous ICI plus background noise is an important issue. Generally, it is assumed that the SCM estimated by using training symbols. However, it is difficult to measure the interference statistics for a long time and training symbol is also not appropriate for MIMO-OFDMA system such as LTE. Therefore, a noise reduction method is required to improve the estimation accuracy. Although the conventional time-domain low-pass type weighting method can be effective for noise reduction, it causes significant estimation error due to the spectral leakage in practical OFDM system. Therefore, we propose a time-domain sinc type weighing method which can not only reduce the noise effectively minimizing estimation error caused by the spectral leakage but also implement frequency-domain moving average filter easily. By using computer simulation, we show that the proposed method can provide up to 3dB SIR gain compared with the conventional method.

• Journal of the Korea Society for Simulation
• /
• v.15 no.1
• /
• pp.35-42
• /
• 2006

Sensor network, that is an infrastructure of ubiquitous computing, consists of a number of sensor nodes of which hardware is very small. The network topology and routing scheme of the network should be determined according to its purpose, and its hardware and software may have to be changed as needed from time to time. Thus, the sensor network simulator being capable of verifying its behavior and estimating performance is required for better design. Sensor network simulators currently existing have been developed for specific hardwares or operating systems, so that they can only be used for such systems and do not provide any means to estimate the amount of power consumption and program execution time which are major issues for system design. In this study, we develop the sensor network simulator that can be used to design and verify various sensor networks without regarding to types of applications or operating systems, and also has the capability of predicting the amount of power consumption and program execution time. For this purpose, the simulator is developed by using machine instruction-level discrete-event simulation scheme. As a result, the simulator can be used to analyze program execution timings and related system behaviors in the actual sensor nodes in detail. Instruction traces used as workload for simulations are executable images produced by the cross-compiler for ATmega128L microcontroller.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.10a
• /
• pp.782-785
• /
• 2011

Needs for MG(Microgrid) development are increasing all over the world as a solution to the problems including the depletion problem of energy resources, the growing demand for electric power and the climatic and environmental change. Especially Photovoltaic power is one of the most general renewable energy resources. However there is a problem of the uniformity of power quality because the power generated from solar light is very sensitive to climate fluctuation (variation of insolation and duration of sunshine, etc). As a solution to the above problem, ESS(Energy Storage System) is considered generally, but it has some limitations. To solve this problem this paper suggests a hybrid estimation method of photovoltaic power generation according to two climatic factors, i.e. insolation and sunshine. This result seems to help design the appropriate capacity of ESS and estimate the proper switching time between DC and AC power in the premises power system and thus maintain the uniformity of power quality.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.2
• /
• pp.430-439
• /
• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.3
• /
• pp.866-872
• /
• 2010

In this paper, we developed a digital soldering station based on PID controller, which supply stable power by controlling the current of heater of soldering iron. The proposed system designed PID controller to converge quickly to the set up temperature by user, and regain the lost of heat by external factors quickly. PID controller, designed by Ziegler-Nichols' tuning method, decides triac's trigger timing using setting temperature and present temperature to control the phase of AC 24V power that supply to the heater. Also, we give the function that shows present temperature and setting temperature of iron, and working time by graphic LCD. And during the rest time, we decided the power saving and extension of iron tip by dropping to the optimal temperature. Two experiments had implemented in $25^{\circ}C$ laboratory to confirm the performance of proposed method. The first experiment took 12sec, 13sec, 16sec, 18sec, reaching to $200^{\circ}C$, $300^{\circ}C$, $400^{\circ}C$, $480^{\circ}C$ respectively which result showed shorten of rising time than previous method. In the loading experiment of $300^{\circ}C$, $400^{\circ}C$, $480^{\circ}C$ steady state showed temperature drop of $3.8^{\circ}C$, $4.1^{\circ}C$, $4.5^{\circ}C$ which result showed the low temperature deviation than previous method.

• Korean Journal of Social Welfare Studies
• /
• v.49 no.2
• /
• pp.5-38
• /
• 2018

The purpose of this study is to examine work-life balance by analyzing time schedules of married couple. The 2014 Korea Time Use Survey dataset was used for the analysis. Finally, 6,262 time diaries of 3,131 households were included in the analysis. The study used sequence analysis in particular, by applying the Lesnard(2014)'s dynamic hamming matching (DHM) method, which is useful for the time diary analysis where timing is a key factor. This study explored daily schedules of each man and woman according to 9 types of couple-combined work-schedules, which had been already derived by cluster analysis. The daily schedules were identified according to the activities divided as labor, housework, sleep, self-management, active leisure, passive leisure, and others. Here, time allocation was analyzed through various graphs showing average time amount and modal states by time period. Based on the analysis, it summarized that "long working hours as a main factor of work-life imbalance", "gender inequality of time use", "non-standard hours work impairing quality of life and "poverty of leisure time"as characteristics of work-life imbalance. Finally this study discussed the social policy implications to support work-life balance.