• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2002.05a
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• pp.60-63
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• 2002

자동 변속기 차량은 여러 가지의 장점을 지니고 있으며, 쉬프트 맵의 특징이 수동 변속기 차량과는 달리 이미 규정된 패턴을 따른다 하지만 킥 다운, 킥 업, 리프트 풋 업 등의 현상이 어느 운전자에게나, 어떤 주행 상황에서나 일괄 적용되고 있기에 불만스러움을 느끼는 운전자가 있을 수 있다. 이에 본 논문에서는 지능형 자동 변속 시스템의 변속 결과에 따른 운전자의 불만 정도를 고려하고 다음 변속에 반영하도록 고안한 만족도 보정 기법을 제안하고자 한다 만족도 평가는 변속이후 운전자의 조작을 관찰하며, 불만족 정도에 따라 최종 쉬프트 선도의 조정을 결정하도록 고안하였으며, 변속 시스템의 변속 결정과 운전자의 스로틀 및 브레이크 조작을 입력으로 한 신경 회로망을 구성하여 학습하였다

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2002.05a
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• pp.149-153
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• 2002

자동 변속기 차량은 여러 가지의 장점을 지니고 있으며, 쉬프트 맵의 특징이 수동 변속기차량과는 달리 이미 규정된 패턴을 따른다. 하지만 킥 다운, 킥 업, 리프트 풋 업 등의 현상이 어느 운전자에게나, 어떤 추행 상황에서나 일괄 적용되고 있기에 불만스러움을 느끼는 운전자가 있을 수 있다. 이에 본 논문에서는 이런 일반적으로 정해진 쉬프트 맵을 운전자의 조작 정도와 차량의 상태를 종합적으로 고려하여 쉬프트 맵을 수정, 적용할 수 있도록 지능형 변속 시스템을 구현하였다. 변속 시스템의 학습 과정에서는 뛰어난 학습 능력을 지니고 있기 때문에 판단 및 추론이 요구되는 지능형 시스템의 학습 도구로 다양하게 적용되고 있는 소프트 컴퓨팅(Soft Computing) 기법을 이용하였으며, 각 학습 내용에 따라 필요 입력을 별도로 구성한 모듈 형태의 망구조를 지니고 있다. .

• Transactions of the Korean Society of Automotive Engineers
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• v.10 no.3
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• pp.201-208
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• 2002

In this paper, the control strategy of ratio changing system for a metal belt CVT adopting primary pressure regulation is developed, and the shirting performance of pressure regulating type CVT with the suggested control strategy is investigated. The control strategy suggested in this study is composed of 2 feedback loop, one is speed ratio feedback and the other is primary pressure feedback. The pressure feedback is adopted to ensure prohibiting a belt slip during transient period in a fast downshift mode. Simulation results show that the system with suggested control strategy gives appropriate response time and tracking Performance for upshift and also gives a proper primary pressure which can prohibit the belt slip. In addition, it is fecund that the given system has an acceptable servo property in tracking the target speed ratio and robustness for the disturbance of line pressure.

• Transactions of the Korean Society of Automotive Engineers
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• v.5 no.5
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• pp.9-19
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• 1997

In this paper, the modeling and analysis of dynamic characteristics has been carried out for friction clutches and brakes in an automatic transmission. From the operating oil pressure generated by the valve-body, time delay by check valve and the movement of piston has been examined. Also torque capacity and torque transferred at the clutch is studied. Heat capacity and temperature distribution at the reaction plate of clutch are codeled by time-dependent, nonhomogeneous partial differential equation, and brake torque, brake time, and the amount of heat generated are investigated. It is found that the time delay at the check valve is very short but dominant at the spool.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.1
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• pp.18-23
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• 2011

We have investigated the Intelligent Shift-map Module(ISM) to improve some problems in the conventional Automatic Transmission(AT) for automobiles. The typical AT lacks flexibility regarding the shift point because it does not consider the driver's habits and inclinations. Also it often is occurred phenomenon like kick-down. Therefore, we designed a decision module which considers the driving style of the individual driver. The driving style was determined by the inclination of the driver and the driving technique using actual automobile data. The Hierarchical Neural Network(HNN) was applied in generating an intelligent shift map with Multilayer Neural Network(MNN). It was found that the proposed ISM provided a suitable shift point and time because the necessary toque and velocity of the automobile was considered along with the driving style of each driver when designing the ISM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).