• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.6
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• pp.626-633
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• 2005

This paper proposes a new 2MVA SSFG(Sag Swell Flicker Generator) injecting voltage by using series inverter. The proposed SSFG composes series inverter, DC capacitor as energy storage, rectifier and voltage clamp circuit. This SSFG is designed to generate typical power disturbances, such as voltage sag/swell, over/under voltage and voltage flicker. Also it is designed to generate unexpected voltage phase jumping waveform by controlling the series inverter. In this paper, three kinds of control methods for the proposed 2MVA SSFG we investigated by PSIM simulation. Also typical voltage sag, swell, flicker waveforms are implemented by adopting effective control method.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.3
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• pp.242-249
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• 2011

The proposed converter has easy device selection for high step-up and high power applications since boost half bridge and voltage doubler cells are connected, respectively, in parallel and series in order to increase output power and voltage. Especially, optimized design of high frequency transformers is possible owing to reduced turn ratio and eliminated dc offset, and distributed power through three cores is beneficial to low profile and thermal distribution. The proposed converter does not necessitate start-up circuit and additional clamp circuit due to the use of whole duty range between 0 and 1 and is suitable for applications with wide input voltage range. Also, high efficiency can be achieved since ZVS turn on of switches are achieved in wide duty cycle range and ZCS turn on and off of diodes are achieved. The proposed converter was validated through 5 kW prototype.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.27-37
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• 1999

A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.