• Proceedings of the Korea Information Processing Society Conference
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• 2016.10a
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• pp.22-25
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• 2016

맵 캐시 기법을 사용하는 낸드 플래시 저장장치는 맵 데이터를 저장하기 위한 공간을 필요로 한다. 이 공간을 맵 블록이라 브르며 시스템 유지 및 성능 개선을 위해 사용되는 낸드 블록의 일부를 점유한다. 맵 블록의 개수가 너무 많을 경우 시스템 유지에 블록이 부족해지기 때문에 전반적인 성능이 하락하게 된다. 하지만 맵 블록이 너무 적은 경우에도 전체 맵 데이터를 유지하기 위한 동작이 과도하게 수행되어 성능이 크게 하락하는 문제가 발생한다. 본 논문은 맵 블록 개수에 따른 성능 변화를 분석하고 최적의 맵 블록 개수를 제안한다.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06a
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• pp.293-295
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• 2012

가상화 기술은 물리적 컴퓨팅 자원을 사용자에게 논리적으로 제공하여 시스템의 효율성을 높이고 유연성을 향상시키기 위한 기술로 서버 통합이나 아마존 EC2와 같은 클라우드 컴퓨팅 환경에서 사용되고 있다. 이러한 가상화 환경에서는 다수의 가상머신들의 동시적인 I/O 수행으로 인해 저장장치에 병목현상이 발생된다. 또한 각 가상머신들의 중복된 데이터들을 저장하기 위해 불필요한 쓰기 비용이 발생하여 시스템의 성능 저하가 발생하게 된다. 본 논문에서는 이러한 가상화 환경에서의 I/O비용을 감소시키기 위해 SSD를 캐시로 사용하는 중복 제거 기법을 제안한다. 제안된 기법은 중복된 데이터를 제거하여 불필요한 디스크에 대한 I/O 수행을 감소시키며, 중복 발생 패턴의 특성을 고려하여 SSD의 빠른 쓰기 성능을 효과적으로 사용할 수 있는 캐시 구조 모델을 통해 가상화 환경에서 I/O 성능을 향상 시킬 수 있음을 보인다.

• The KIPS Transactions:PartC
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• v.12C no.3 s.99
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• pp.443-448
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• 2005

Efficient using of the web cache is becoming important factors that decide system management efficiency in the web base system. The cache performance depends heavily on the replacement algorithm which dynamically selects a suitable subset of objects for caching in a finite cache space. In this paper, the web caching algorithm is proposed for the efficient operation of the web base system. The algorithm is designed based on a divided scope that considered size reference characteristic and heterogeneity on web object. With the experiment environment, the algorithm is compared with conservative replacement algorithms, we have confirmed more than $15\%$ of an performance improvement.

• Journal of Advanced Navigation Technology
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• v.14 no.6
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• pp.916-927
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• 2010

In this paper, we analyze the performance of the parity cache enabled RAID level-5 via the simulation. This RAID system consists of the DDR memory-based storage devices. To do this, we develop the simulation model and suggest the basic performance analysis data which we want to get via the simulation. And we implement the simulator based on the simulation model and execute the simulator. From the result of the simulation, we expect that the parity cache enabled RAID level-5 configured by the DDR memory based storage devices has the positive effectiveness to the enhancing of the storage system performance if the storage access patterns of applications are tuned.

• Journal of KIISE
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• v.42 no.8
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• pp.972-978
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• 2015

Non-volatile memory (NVM) supports both byte addressability and non-volatility. These characteristics make it feasible for NVM to be employed at any layer of the memory hierarchy such as cache, memory and disk. An interesting characteristic of NVM is that, even though it supports non-volatility, its retention capability is limited. Furthermore NVM has tradeoff between its retention capability and write latency. In this paper, we propose a novel NVM-based file cache management scheme that makes use of the limited retention capability to improve the cache performance. Experimental results with real-workloads show that our scheme can reduce access latency by up to 31% (24.4% average) compared with the conventional LRU based cache management scheme.

• Journal of KIISE
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• v.44 no.12
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• pp.1245-1251
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• 2017

In this study we present a novel directory architecture that can dynamically allocate a directory entry for a cache block on demand at runtime only when the block is shared by more than one core. Thus, we do not maintain coherence for private blocks, substantially reducing the number of directory entries. Even for shared blocks, we allocate directory entry dynamically only when the block is actively shared, further reducing the number of directory entries at runtime. For this, we propose a new directory architecture called dynamic directory table (DDT), which is implemented as a cache of active directory entries. Through our detailed simulation on PARSEC benchmarks, we show that DDT can outperform the expensive full-map directory by a slight margin with only 17.84% of directory area across a variety of different workloads. This is achieved by its faster access and high hit rates in the small directory. In addition, we demonstrate that even smaller DDTs can give comparable or higher performance compared to recent directory optimization schemes such as SPACE and DGD with considerably less area.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.101-110
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• 1997

SVLIW processor architectures can resolve resource collisions and data dependencies between the instructions while scheduling VLIW instructions at run-time. As a result, long NOP word instructions can be removed from the object code produced for the processor. Thus, the occurrence of cache misses on the SVLIW processor would be lesser than that on the same cache size VLIW processor. Less frequent cache misses on the SVLIW processor would incur less frequent memory access, and thus, the total execution cycles to complete an application would be shortened compared with cases on the VLIW processor. Such a feature eventually compromises effects of longer instruction pipeline stages than those of the VLIW processor. In this paper, we formulate and compare two execution cycle models of the two architectures. A simulation results show that the longer memory access cycles when cache miss occurs, the total execution cycles of SVLIW processor would be shorter than those of VLIW processor.

• Journal of KIISE
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• v.42 no.11
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• pp.1314-1321
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• 2015

Mobile devices employ buffer cache mechanisms, just as in computer systems such as desktops or servers, to mitigate the performance gap between main memory and secondary storage. However, DRAM has a problem in that it accelerates battery consumption by performing refresh operations periodically to maintain the stored data. In this paper, we propose a novel buffer cache scheme to increase the battery lifecycle in mobile devices based on a hybrid main memory architecture consisting of DRAM and non-volatile PCM. We also suggest a new buffer cache policy that allocates buffers based on process states to optimize the performance and endurance of PCM. In particular, our algorithm allocates each page to the appropriate position corresponding to the state of the application that owns the page, and tries to ensure a rapid response of foreground applications even with a small amount of DRAM memory. The experimental results indicate that the proposed scheme reduces the elapsed time of foreground applications by 58% on average and power consumption by 23% on average without negatively impacting the performance of background applications.

• Journal of KIISE:Databases
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• v.30 no.4
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• pp.408-419
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• 2003

Data warehouses are usually dedicated to the processing of quires issued by decision support system(DSS). The response time of DSS queries is typically several orders of magnitude higher than the one of OLTP queries. Since DSS queries are often submitted interactively, techniques for reducing their response time are important. The caching of query results is one such technique particularly well suited to the DSS environment. In this paper, we present a cache manager for such an environment. Specifically, we define a canonical form of query. The cache manager looks up a query based on the exact query match or using a suggested query split process if the query is found is non-canonical form or in canonical form, respectively. It dynamically maintains the cache content by employing a profit function which reflects in an integrated manner the query execution cost, the size of query result, the reference rate, the maintenance cost of each result due to updates of their base tables, and the frequency of such updates. We performed the experimental evaluation and it positively shows the performance benefit of our cache manager.

• KIPS Transactions on Computer and Communication Systems
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• v.10 no.12
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• pp.319-328
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• 2021

With popularization of services for massive content, the fundamental limitations of TCP/IP networking were discussed and a new paradigm called Information-centric networking (ICN) was presented. In ICN, content is addressed by the content identifier (content name) instead of the location identifier such as IP address, and network nodes can use the cache to store content in transit to directly service subsequent user requests. As the user request can be serviced from nearby network caches rather than from far-located content servers, advantages such as reduced service latency, efficient usage of network bandwidth, and service scalability have been introduced. However, these advantages are determined by how actively content stored in the cache can be utilized. In this paper, we 1) introduce content access schemes in Named-data networking, one of the representative ICN architectures; 2) in particular, review the schemes that allow access to cached content away from routing paths; 3) conduct comparative study on the performance of the schemes using the ndnSIM simulator.