• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1982-1990
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• 1994

We implemented a PLDRO(Phase Locked Dielectric Resonator Oscillator) using the concept of the feedback property of PLL(Phase Locked Loop) for Ku-band(10.95-11.70 GHz). The conventional approaches to a PLDRO design use varactor diode tuning method.. But in theis paper, the PLDRO has the advantage of the frequency sensitivity to changes in the supple voltage of the oscillating device without the frequency-variable part by varactor diode voltage-control. and uses a SPD(Sampling Phase Detector) for phase-comparision. The PLDRO is composed of the DRO phase-locked to the reference signal of UHF band by using a SPD for high frequency stability and can be available for European FSS(Fixed Satellite Service) at 10.00GHz. The PLDRO generates the output power of 8.67 dBm at 10.00 GHz and has a phase noise of -81 dBc/Hz at 10 kHz offset from carrier. The hamonic and spurious characteristics have -42.33 dBc and -65dBc respectively. This PLDRO has much better frequency stability, lower phase noise, and more economical effect for a satellite system than conventional DRO.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.5
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• pp.510-518
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• 2010

In this paper, the designed and implemented results of CFL linearization chip which can be used in mobile radio and TRS terminal of UHF band(380~910 MHz), using $0.6\;{\mu}m$ BiCMOS process based on Si, are shown. As gain control circuits for modifying transmit power are inserted not only in feedback path but also in forward path, the stability of CFL is maintained. And, DC-offset correction function of S/H structure, which is suitable for walkie-talkie PTT operation and is easily implemented, is realized. The performance test results of transmitter show that the regulation of FCC emission mask at PEP 3 W(34.8 dBm) is satisfied when the CQPSK modulated signal is fed and more than 30 dBc improvement of 3rd order IMD is achieved when two-tone signal is inputted.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.12
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• pp.1380-1387
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• 2012

The transmit/receive(T/R) module is a key component in the active phased array system. The brick-type T/R module has been widely used and the miniaturization has been an important factor to get the flexibility of the system configuration. For the miniaturization, multi-function chips(MFC) having a common leg configuration are suitable to reduce the number of required MMICs and a high isolation between transmit and receive paths is necessary for the high gain T/R modules. In this work, we propose a bias timing scheme for the compact T/R module and show the optimum timing based on measurements, in order to improve the feed-back path loop problem and the consequent isolation problem of the common leg configuration. We have implemented high power(7 W/channel) and high T/R gain(35 dB transmit and 30 dB receive gains) within the half size($140{\times}80{\times}16mm^3$) of the conventional T/R modules.

• Journal of Navigation and Port Research
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• v.30 no.10 s.116
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• pp.847-853
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• 2006

In this paper, we designed VCO(voltage controlled oscillator} that is composed of a dielectric resonator and a varactor diode, and the PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The results at 12.05 GHz show the output power is 13.54 dBm frequency tuning range approximately +/- 7.5 MHz, and power variation over the tuning range less than 0.2 dB, respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 dBc/Hz at 100 kHz offset from carrier, and The second harmonic suppression is less than -41.49 dBc. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.25-32
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• 2005

In this papers, we first, therefore, designed VCO(voltage controlled oscillator) that is composed of the dielectric resonator and the varactor diode, and then designed and fabricated PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The measured results of the fabricated PLDRO at 12.05 [GHz] show the output power is 13.54 [dBm], frequency tuning range approximately +/- 7.5 [MHz], and Power variation over the tuning range less than 0.2 [dB], respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 [dBc/Hz] at 100 [KHz] offset from carrier, and The second harmonic suppression is less than -41.49 [dBc]. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.