• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.983-986
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• 2000

본 논문에서는 저전압(2V) 동작이 가능하도록 완전차동 구조의 아날로그 능동소자에 전압조절을 위한 튜닝 회로를 추가한 능동소자를 제안하였다. 아날로그 능동소자는 이득특성에 영향을 주는 트랜스컨덕턴스값을 증가시키기 위해 CMOS 상보형 캐스코드 방식을 이용하여 구성되었다. 0.25㎛ CMOS n-well 공정 파라미터를 이용한 HSPICE 시뮬레이션 결과, 제안된 아날로그 능동소자는 비우성극점의 제거로 안정성이 향상되었으며, 2V 공급전압하에서 42dB의 이득값과 200MHz의 단위 이득주파수 특성을 나타내었다. 소비전력값은 0.32mW를 나타내었다.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.164-167
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• 2010

`신호 공간 다이버시티(Signal Space Diversity)'기술은 DVB-T2 표준에 포함된 기술로써, 추가적인 전력이나 대역폭의 희생없이 검파에 있어 성능 이득을 얻을 수 있어 DVB-T2 물리계층 핵심적인 기술 중 하나로 평가받으며, 후속 표준인 DVB-NGH 에도 적용 가능성이 높은 기술이다. 본 논문에서는 '신호 공간 다이버시티' 기술을 MIMO 시스템으로 확장하기 위해서 발생하는 문제점에 대해서 분석한 뒤, 이를 해결하기 위해 제안된 '성분 맞교환(Component-Swapping)' 기술을 현재 논의 중에 있는 DVB-NGH 시스템에 적용하여 주어진 실험 환경에서 2.2~3.0dB 가량의 이득을 가짐을 실험적으로 확인하였다.

• Journal of the Korea Society of Computer and Information
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• v.9 no.2
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• pp.89-96
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• 2004

In this paper, an improved method is proposed by supplementing multi-path gain for detection. This method is proposed to complement the shortcomings of the conventional detection method which is used for multiuser detection in STBC(Space-Time Block Code) CDMA system. We analyzed the improved method in bit error probability viewpoint and compared the result with that of the conventional method. From this result, we showed that bit error probability of the improved method is superior to that of the conventional method when the parameters such as delay, number of user and SNR are increased.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.6
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• pp.891-896
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• 2002

In this paper, a new voltage-controlled tunable integrator for low-voltage applications is proposed. The proposed active element is composed of the CMOS complementary cascode circuit which can extend transconductance of an element. Therefore, the unity gain frequency which is determined transcon-ductance is increased than that of the conventional element. And then these results are verified by the $0.25{\mu}m$ CMOS n-well parameter HSPICE simulation. As a result, the gain and the unity gain frequency are 42dB and 200MHz respectively in the element on 2V supply voltage. And power dissipation of the designed circuit is 0.32mW.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.11a
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• pp.49-52
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• 2011

본 논문에서는 구간선형 모델을 적용하여 낮은 복잡도를 가지는 LSC(Lens-Shading Correction) 알고리즘을 제안한다. 제안한 알고리즘은 각 화소와 렌즈 중심점으로부터 거리를 정수형으로 계산하고, 이 정수를 거리에 대한 LSC 이득값이 저장된 LUT(Look-Up Table)에 대한 주소로 적용하여, 입력 화소 값에 곱함으로써 LSC를 수행한다. 거리를 구하려면 제곱근 회로가 추가되어야 한다. LUT에 저장된 이득값은 원점으로부터의 거리에 대한 평균 이득값을 저장하고 있기 때문에, 제곱근 계산에 높은 정밀도를 할애하여도 LSC 보상된 영상의 화질에 미치는 영향은 높지 않으므로 정수형 제곱근 연산을 수행한다. 제곱근 계산은 구간 선형화하여 단지 덧셈과 쉬프트 연산만으로 제곱근 연산을 완료할 수 있도록 간략화 하였다. 제안한 알고리즘을 양산 중인 일반 카메라 모듈에 적용한 결과, 카메라모듈 제조업체의 LSC 평가 기준을 상회하는 수준으로 나타나며, 구현될 하드웨어 복잡도가 매우 낮아서 모바일 카메라 구현에 매우 적합하다.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1508-1509
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• 2007

본 논문에서는 TSMC 0.18um공정을 이용한 무선통신 수신기용 직접변환 방식의 Double Balanced Mixer를 설계 하였다. 제안된 mixer는 current bleeding기법과 내부에 인덕터를 추가하여 기존의 Gilbert Cell구조의 mixer에 비해 변환 이득과 Flicker Noise특성을 향상 시켰다. 모의실험결과 2.45GHz에서 11dB의 변환이득을 나타내었으며 Flicker Noise의 corner frequency는 510kHz이고 이때 잡음특성은 10.8dB이다. 이 회로의 동작전압은 1.8V이며 소모 전력은 8.8mW이다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.16-23
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• 2003

In this paper, we propose an efficient bias circuit of discrete BJT component for hearing aid. The collector feedback bias circuit, widely used for the hearing aid, has a resistor for negative feedback. As the resistor affects AC and DC simultaneously, it is quite difficult to adjust amplifier gain without changing DC bias point. The previous bias circuit also has weak point to be oscillated by the positive feedback of power noise if gain of hearing aid is high. In the proposed circuit, we can reduce the two weak points of the previous circuit by adding a resistor to the collector feedback bias circuit between base and power supply which is $\beta$ times target than the collector resistor. Thus. we can change amplifier gain without changing DC bias point, and reduce power noise gain about 18.5% compare to that of tile previous circuit in the simulation.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1477-1483
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• 2013

This paper proposes a low-voltage current-mode integrator for a continuous-time current-mode baseband channel selection filter. The low-voltage current-mode linear cascode integrator is introduced to offer advantages of high current gain and improved unity-gain frequency. The proposed current-mode integrator has fully differential input and output structure consisting of CMOS complementary circuit. Additional cascode transistors which are operated in linear region are inserted for bias to achieve the low-voltage feature. Frequency range is also controllable by selecting proper bias voltage. From simulation results, it can be noticed that the implemented integrator achieves design specification such as low-voltage operation, current gain, and unity gain frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.16-23
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• 2009

A 12b 10MS/s pipelined ADC with low DC gain amplifiers is presented. The pipelined ADC using a reference scaling technique is proposed to compensate the gain error in MDACs due to a low DC gain amplifier. To minimize the performance degradation of the ADC due to amplifier offset, the proposed offset trimming circuit is employed m the first-stage MDAC amplifier. Additional reset switches are used in all MDACs to reduce the memory effect caused by the low DC gain amplifier. The measured differential and integral non-linearities of the prototype ADC with 45dB DC gain amplifiers are less than 0.7LSB and 3.1LSB, respectively. The prototype ADC is fabricated in a $0.35{\mu}m$ CMOS process and achieves 62dB SNDR and 72dB SFDR with 2.4V supply and 10MHz sampling frequency while consuming 19mW power.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.10
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• pp.1855-1861
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• 2017

In this paper, the gain enhancement of an SDPA using a director and two parasitic patches is studied. The modified balun is used to increase the bandwidth, whereas the director and two parasitic patches are appended to the SDPA to enhance the gain in the middle and high frequency bands. The effects of the distance between the director and parasitic patches on the antenna performance are analyzed, and the SDPA with a gain over 7 dBi at 1.54-2.99 GHz band is designed. The proposed SDPA is fabricated on an FR4 substrate with a dimension of $90mm(L){\times}135mm(W)$ in order to validate its performance. The fabricated antenna shows a frequency band of 1.56-3.10 GHz for a VSWR < 2, and it is confirmed by measurement that gain maintains over 7 dBi in the frequency range of 1.54-3.00 GHz.