• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.6 no.3
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• pp.165-173
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• 2007

In this paper, we propose a new minimum resources allocation algorithm for optimal design automation. In the proposed algorithm, the operation are allocated to functional units so that the number of interconnection wires between functional units can be minimized. The registers are allocated to the maximal clusters generated by the minimal cluster partitioning algorithm. Finally, the interconnection is minimized by removing the duplicated inputs of multiplexers and exchanging the inputs across multiplexers. The efficiency of the proposed allocation algorithm is shown by experiments using benchmark examples.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9A
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• pp.1401-1410
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• 1999

In this paper, we propose a fast block matching algorithm using the lower and upper bound of mean absolute difference (MAD) which is calculated at the search region overlapped with neighbor blocks. At first, we calculate the lower bound of MAD and reduce the search point by using this lower bound. In this method, we can get good prediction error performance close to full search block matching algorithm (FSBMA), but there exists some computational complexity that has to be reduced. Therefore, we further reduce the computational complexity by using pixel subsampling besides the lower and upper bound of MAD. Experimental results show that we can remarkably reduce the computational complexity with good prediction error performance close to FSBMA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.7B
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• pp.996-1005
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• 2001

본 논문에서는 ASIC 벤더의 셀 라이브러리와 MUX-based FPGA에 있는 고정된 입력을 갖는 연결구조의 수를 최소화하는 하드웨어 할당 알고리듬을 제안한다. 제안된 할당 알고리듬은 연산자간을 연결하는 신호선이 반복적으로 이용되어 연결 신호선 수가 최소가 될 수 있도록 연산자를 할당한다. 연결 구조를 고려한 이분할 그래프에 가중치를 설정하고 변수와 레지스터간의 최대 가중치 매칭을 구함으로써 레지스터 할당을 수행한다. 또한 연결구조에 대한 멀티플렉서의 중복 입력을 제거하고 연산자에 연결된 멀티플렉서간의 입력을 교환하는 입력 정렬 과정으로 연결구조를 최소화한다. 벤치마크 실험을 통하여 제안된 알고리즘의 효용성을 보인다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.9
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• pp.995-1000
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• 2016

The maximum cross-correntropy (MCC) algorithm with a set of random symbols keeps its optimum weights undisturbed from impulsive noise unlike MSE-based algorithms and its main factor has been known to be the input magnitude controller (IMC) that adjusts the input intensity according to error power. In this paper, a normalization of the step size of the MCC algorithm by the power of IMC output is proposed. The IMC output power is tracked recursively through a single-pole low-pass filter. In the simulation under impulsive noise with two different multipath channels, the steady state MSE and convergence speed of the proposed algorithm is found to be enhanced by about 1 dB and 500 samples, respectively, compared to the conventional MCC algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.241-248
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• 2007

In predictive image coding, a LS (Least Squares)-based adaptive predictor is an efficient method to improve image edge predictions. This paper proposes a hybrid interpolation with weighted edge detector. A hybrid approach of switching between bilinear interpolation and EDI (Edge-Directed Interpolation) is proposed in order to reduce the overall computational complexity The objective and subjective quality is also similar to the bilinear interpolation and EDI. Experimental results demonstrate that this hybrid interpolation method that utilizes a weighted edge detector can achieve reduction in complexity with minimal degradation in the interpolation results.

• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.3
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• pp.174-179
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• 2007

In this paper, we present a optimal module selection using genetic algorithm under the power, area, delay constraint. The proposed algorithm use the way of optimal module selection it will be able to minimize power consumption. In the comparison and experimental results, The proposed application algorithm reduce maximum power saving up to 26.9% comparing to previous non application algorithm, and reduce minimum power saving up to 9.0%. It also show the average power saving up to 15.525% and proved the power saving efficiency.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1998.10a
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• pp.275-277
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• 1998

최근 Ravi와 Goemanns는 즉 전체 길이의 합이 일정한 값을 넘지 않는 최소비용신장나무(minimum spanning tree problem)를 구하는 문제의 (1+$\varepsilon$,1)-근사해를 구할 수 있는 알고리듬을 제시하였다. 즉 비용은 최적을 보장하지만 전체길이 제약조건은 근사적으로 만족하는 해를 생성한다. 그러나 이러한 알고리듬은 문제의 비가능해를 생성 할 수 있으며 1/$\varepsilon$에 대하여 지수함수의 수행시간을 갖는다. 본 논문에서는 Ravi와 Geomanns의 알고리듬을 실용적으로 변형하여 전체 길이 제약조건을 정확히 만족하며, 그 비용은 최적비용과의 차이가 호의 비용 중 최대값을 넘지 않도록 보장하는 강성다항식 알고리듬을 제사한다.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.339-343
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• 2001

본 연구에서는 수중 음의 전달에 작용하는 기하와 지음향 매개변수들을 전역 최적화(global optimization) 방법인 유전자 알고리듬을 사용하여 추정하려한다. 유전자 알고리듬은 목적함수가 불규칙적인 경우에도 모든 가능한 매개변수들을 조사하지 않으면서 전역 최대치 또는 최소치를 추정할 수 있는 최적화 방법으로, 정합장처리와 관련된 매개변수의 조사에 적합한 방향성 조사법이라 할 수 있다. 유전자 알고리듬을 이용하여 천해 해양환경에서 수치실험을 통해 매개변수 역산의 가능성을 살펴보도록 하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.1
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• pp.1-7
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• 2017

The maximum zero error probability (MZEP) algorithm outperforms MSE (mean squared error)-based algorithms in impulsive noise environment. The magnitude controlled input (MCI) which is inherent in that algorithm is known to plays the role in keeping the algorithm undisturbed from impulsive noise. In this paper, a new approach to normalize the step size of the MZEP with average power of the MCI is proposed. In the simulation under impulsive noise with the impulse incident rate of 0.03, the performance enhancement in steady state MSE of the proposed algorithm, compared to the MZEP, is shown to be by about 2 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.