• Journal of the Korea Society of Computer and Information
• /
• v.14 no.10
• /
• pp.1-10
• /
• 2009

Precise branch predictor has a profound impact on system performance in modern processor architectures. Recent works show that prediction latency as well as prediction accuracy has a critical impact on overall system performance as well. However, prediction latency tends to be overlooked. In this paper, we propose Branch Pre-Prediction policy to tolerate branch prediction latency. The proposed solution allows that branch predictor can proceed its prediction without any information from the fetch engine, separating the prediction engine from fetch stage. In addition, we propose newly modified BTE structure to support our solution. The simulation result shows that proposed solution can hide most prediction latency with still providing the same level of prediction accuracy. Furthermore, the proposed solution shows even better performance than the ideal case, that is the predictor which always takes a single cycle prediction latency. In our experiments, IPC improvement is up to 11.92% and 5.15% in average, compared to conventional predictor system.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.37B no.12
• /
• pp.1113-1118
• /
• 2012

Smart grid and intelligent transportation system draw significant interest since they are considered as one of the green technologies. These systems require a large number of sensors, actuators, and controllers. Also, machine-to-machine (M2M) communications is important because of the automatic control. The LTE-Advanced networks is preparing a set of functions that facilitate the M2M communications, and particularly the development of an efficient call admission control mechanism is critical. A method that groups MTC devices according to QoS constraints and determines the admission depending on the QoS satisfaction is limitedly applied only if the data transmission period and the maximum delay are identical. This paper proposed a call admission control that is free from such limitation and also optimizes the admission process under the certain condition of the transmission period and maximum delay. The theorems regarding the proposed method are presented with the proofs. The simulations confirms its validity and shows it is better in call admission probability than existing works.

• Journal of Advanced Navigation Technology
• /
• v.18 no.5
• /
• pp.501-507
• /
• 2014

A dynamic system is called positive if any trajectory of the system starting from non-negative initial states remains forever non-negative for non-negative controls. In this paper, new sufficient conditions for asymptotic stability of the interval positive time-varying linear discrete-time systems with time-varying delay in states are considered. The considered time-varying delay time has an interval-like bound which has minimum and maximum delay time. The proposed conditions are established by using a solution bound of the Lyapunov equation and they are expressed by simple inequalities which do not require any complex numerical algorithms. An example is given to illustrate that the new conditions are simple and effective in checking stability for interval positive time-varying discrete systems.

• Proceedings of the Korean Society of Propulsion Engineers Conference
• /
• 1997.11a
• /
• pp.14-14
• /
• 1997

추진제의 노화 못지 않게 점화제의 노화도 추진 기관 성능에 큰 영향을 미칠 것으로 예측된다. 따라서 10년 이상 경과된 활성 모터에서 점화기를 분해하여 노화에 의한 점화제의 성능 변화를 알아보았다. 분석에 사용한 점화제는 II-D Bi-Convex형상의 B-KNO$_3$ 펠렛으로 열량, 자동 점화온도, 기계적 물성의 변화를 관찰하였고, 밀폐 용기(Closed bomb)에서 연소시험을 통하여 노화에 따른 점화알약의 압력변화를 측정하고 이론 값과 비교하였다. 또한 비활성 모타를 이용한 연소시험으로 점화기의 점화지연시간, 최대 압력, 최대 압력 도달시간 등을 측정하고 이론식과 비교하여 노화에 의한 변화를 관찰하였다.

• Proceedings of the Korean Society of Propulsion Engineers Conference
• /
• 1998.04a
• /
• pp.25-25
• /
• 1998

진동시험기를 사용한 충격시험은 자유 낙하식 충격시험기를 이용하는 것 보다 여러 가지 장점이 있으며, 충격반응 스펙트럼 시험의 요구가 점점 증가하고 있다. 진동시험기를 이용하여 충격반응 스펙트럼 시험을 실시하는데 진동시험기에서 허용하는 최대 힘, 속도, 변위에 의하여 제약을 받게 된다. 충격반응 스펙트럼을 만족하는 충격파형은 무수히 많으나 최대 가속도, 속도, 변위 등이 작으면 작을수록 그 충격파형의 품질이 우수하다고 말할 수 있다. 충격 지속시간이 짧고 충격가속도의 최대치가 큰 충격파형을 인가할 수 없지만, 충격 지속시간이 보다 길고 충격가속도의 최대치가 작은 파형이 동일한 충격반응 스펙트럼 규격을 만족할 수 있다. 진동시험기를 사용하여 충격반응 스펙트럼 시험을 수행하기 위한 충격파형이 웨이브레트를 이용하여 시험규격의 충격반응 스펙트럼을 만족하도록 합성된다. 웨이브레트의 매개변수는 주파수, 반파의 개수, 지연시간, 극성이다. 각 웨이브레트의 진폭은 시험규격의 충격반응 스펙트럼을 만족하도록·반복적으로 조절된다. 이렇게 합성된 충격파형은 진동시험기를 사용한 충격반응 스펙트럼 시험의 참조 가속도 파형으로 간주된다.

• Journal of Digital Contents Society
• /
• v.7 no.3
• /
• pp.207-210
• /
• 2006

A synchronized multimedia presentation consists of a collection of objects, with each object having one or more rendering intervals within the presentation timeline. These intervals specify the objects' start times and end times relative to the presentation timeline. In this paper we consider the problem of streaming a multimedia presentation from a server to a client over a bandwith-limited communication network. We suppose that each of the static objects is layered-encoded. For a given maximum delay, we consider the problem of finding the optimal number of quality of the presentation. We devise efficient algorithms for determining an optimal policy for several criteria. We also consider the problem of gradual rendering of objects after their start times.

• Annual Conference of KIPS
• /
• 2001.04a
• /
• pp.363-366
• /
• 2001

LILI-128 스트림 암호는 IMT-2000 무선단말간 데이터 암호화를 위하여 제안된 128-비트 크기의 스트림 암호방식이며, 클럭 조절형태의 채택에 따라 속도저하라는 구조적인 문제점을 안고 있다. 본 논문에서는 귀환/이동에 있어서 랜덤한 4개의 연결 경로를 갖는 4-비트병렬 $LFSR_{d}$를 제안함으로서 속도문제를 해결하였다. 그리고 ALTERA 사의 FPGA 소자(EPF10K20RC240-3)를 선정하여 그래픽/VHDL 하드웨어 구현 및 타이밍 시뮬레이션을 실시하였으며, 50MHz 시스템 클럭에서 안정적인 50Mbps (즉, 45 Mbps 수준인 T3급 이상, 설계회로의 최대 지연 시간이 20ns 이하인 조건) 출력 수열이 발생될 수 있음을 확인하였다. 마지막으로, FPGA/VHDL 설계회로를 Lucent ASIC 소자 ($LV160C,\;0.13{\mu}m\;CMOS\;&\;1.5v\;technology$)로 설계 변환 및 타이밍 시뮬레이션한 결과 최대 지연시간이 1.8ns 이하였고, 500 Mbps 이상의 고속화가 가능함을 확인하였다.

• Convergence Security Journal
• /
• v.16 no.7
• /
• pp.113-120
• /
• 2016

This paper presents a new high-speed SHA-1 pipeline architecture having a computation delay close to the maximum critical path delay of the original SHA-1. The typical SHA-1 pipelines are based on either a hash operation or unfolded hash operations. Their throughputs are greatly enhanced by the parallel processing in the pipeline, but the maximum critical path delay will be increased in comparison with the unfolding of all hash operations in each round. The pipeline stage logics in the proposed SHA-1 has the latency is similar with the result of dividing the maximum threshold delay of a round by the number of iterations. Experimental results show that the proposed SHA-1 pipeline structure is 0.99 and 1.62 at the operating speed ratio according to circuit size, which is superior to the conventional structure. The proposed pipeline architecture is expected to be applicable to various cryptographic and signal processing circuits with iterative operations.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.18 no.2
• /
• pp.169-176
• /
• 2018

In this paper, we consider duty-cycled wireless sensor networks (WSNs) in which sensor nodes are periodically dormant in order to reduce energy consumption. In such networks, as the duty cycle interval increases, the energy consumption decreases. However, a higher duty cycle interval leads to the increase in the end-to-end (E2E) delay. Many applications of WSNs are delay-sensitive and require packets to be delivered from the sensr nodes to the sink with delay requirements. Most of existing studies focus on only reducing the E2E delay, rather than considering the delay bound requirement, which makes hard to achieve the balanced performance between E2E delay and energy consumption. A few study that considered delay bound requirement require time synchronization between neighboring nodes or a specific distribution of deployed nodes. In order to address limitations of existing works, we propose a duty-cycle scheduling algorithm that aims to achieve low energy consumption, while satisfying the delay requirements. To that end, we first estimate the probability distribution for the E2E delay. Then, by using the obtained distribution we determine the maximal duty cycle interval that still satisfies the delay constraint. Simulation results show that the proposed design can satisfy the given delay bound requirements while achieving low energy consumption.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.8
• /
• pp.1663-1668
• /
• 2005

There have been numerous researches regarding the QoS guarantee in packet switching networks. IntServs, based on a signaling mechanism and scheduling algorithms, suggesting promising solutions, yet has the crucial complexity problem so that not enough real implementations has been witnessed. Flow aggregation is suggested recently to overcome this issue. In order to aggregated flows fairly so that the latency of the aggregated flows is bound, however, a non-work conserving scheduler is necessary, which is not very popular because of its another inherent complexity. We suggest a non-work conserving scheduler, the Round Robin with Virtual Flow (RRVF), which is a variation of the popular Deficit Round Robin (DRR). We study the latency of the RRVF, and observe that the non-work conserving nature of the RRVF yields a slight disadvantage in terms of the latency, but after the aggregation the latency is greatly reduced, so that e combined latency is reduced. We conclude that the flow aggregation through RRVF can actually reduce the complexity of the bandwidth allocation as well as the overall latency within a network.