• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.1 no.2
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• pp.4-18
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• 2002

In this paper, we propose the new design method for the OFDM based modem that is considerd a standard of wireless communication in indoor environments. We designed a improved FFT/IFFT in order to satisfy a data rate $6{\sim}54$Mbps required homenetworking of high speed and a improved channel equalization circuit using pilot signals for modile environments. And we designed a carrier offset estimator that uses the $tan^{-1}$ circuit to organize a memory structure. All steps are verifed performance through a FPGA and are implemented ASIC to use a standard library cell.