• Nuclear Medicine and Molecular Imaging
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• v.43 no.5
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• pp.468-477
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• 2009

Purpose: Hydrodynamic-based procedure is a simple and effective gene delivery method to lead a high gene expression in liver tissue. Non-invasive imaging reporter gene system has been used widely with herpes simplex virus type 1 thymidine kinase (HSV1-tk) and its various substrates. In the present study, we investigated to image the expression of HSV1-tk gene with 5-(2-iodovinyD-2'-deoxyuridine (IVDU) in mouse liver by the hydrodynamicbased procedure. Materials and Methods: HSV1-tk or enhanced green fluorescence protein (EGFP) encoded plasmid DNA was transferred into the mouse liver by hydrodynaminc injection. At 24 h post-injection, RT-PCR, biodistribution, fluorescence imaging, nuclear imaging and digital wholebody autoradiography (DWBA) were performed to confirm transferred gene expression. Results: In RT-PCR assay using mRNA from the mouse liver, specific bands of HSV1-tk and EGFP gene were observed in HSV1-tk and EGFP expressing plasmid injected mouse, respectively. Higher uptake of radiolabeled IVDU was exhibited in liver of HSV1-tk gene transferred mouse by biodistribution study. In fluorescence imaging, the liver showed specific fluorescence signal in EGFP gene transferred mouse. Gamma-camera image and DWBA results showed that radiolabeled IVDU was accumulated in the liver of HSV1-tk gene transferred mouse. Conclusion: In this study, hydrodynamic-based procedure was effective in liver-specific gene delivery and it could be quantified with molecular imaging methods. Therefore, co-expression of HSV1-tk reporter gene and target gene by hydrodynamic-based procedure is expected to be a useful method for the evaluation of the target gene expression level with radiolabeled IVDU.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.5
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• pp.509-517
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• 2001

Full-search algorithm requires large amount of computation which causes time delay or very complex hardware architecture for real time implementation. In this paper, we propose a fast motion estimator based on bit-plane matching, which reduce the computational complexity and the hardware cost. In the proposed motion estimator, the conventional motion estimation algorithms are applied to the binary images directly extracted from the video sequence. Furthermore, in the proposed VLSI motion estimator, we employ a Pair of processing cores that calculate the motion vector continuously By controlling the data flow in a systolic fashion using the internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and adopt lower-cost fabrication technology. We modeled and tested the proposed motion estimator in VHDL, and then synthesized the whole system which has been integrated in a 0.6-$\mu$m triple-metal CMOS chip of size 8.15 X 10.84$\textrm{mm}^2$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.9
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• pp.4152-4158
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• 2012

The Stereo X-ray inspection system is designed for effectively providing the additional information of objects than the conventional inspection system that offers only 2D cross-section of objects. We studied the geometric improvement of the stereo X-ray inspection system, the stereo matching algorithm of the single object using the edge and the volume reconstruction method for the inspected object. In this paper, we conduct a matching algorithm to find the correspondences between the images and reconstruct 3-D shapes of real objects using the stereo X-ray images. Also, we apply a new 3D reconstruction algorithm for the discrimination of two objects. For the separation of the overlapping objects, we calculate the vector of the object and divide inner and outer voxel of objects. And for the elimination of the overlapping area, we study the reconstruct 3D shapes using the threshold based Z-axis. The experimental results show that the proposed technique can enhance the accuracy of stereo matching and give more efficient visualization for overlap objects in the restricted environment.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.22-29
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• 1998

In this paper, an 10 bit current-mode CMOS A/D converter with a current predictor is designed with a CMOS process to be integrated into a portable image signal processing system. A current predictor let the number of comparator reduce to 70 percent compared with the two step flash architecture. The current magnitude of current reference is reduced to 68 percent with a modular current reference. The designed 10 bit Low-power current-mode CMOS A/D converter with a current predictor is simulated with HSPICE using 0.6$\mu\textrm{m}$ N-well single-poly triple-metal CMOS process parameters. It results in a conversion rate of 10MSamples/s. A power consumption is measured to be 94.4mW at single +5V supply voltage. The 10 bit A/D converter fabricated using the same process occupies the chip area of 1.8mm x 2.4mm.

• The Korean Journal of Quaternary Research
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• v.20 no.2
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• pp.1-10
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• 2006

Flooding hazard caused by natural and artificial environmental changes is closely associated with change in river bed configuration. This study is aimed at explaining a river-bed change related to soil erosion in the Keum river basin using GIS and RS. The USLE was used to compute soil erosion rate on the basis of GIS. River-bed profiles stretching from Kongju to Ippo were measured to construct a 3D-geomorphological map. The river-bed change was also detected by remote sensing images using Landsat TM during the period of 1982 to 2000 for the Keum river. The result shows that USLE indicates a mean soil erosion rate of $1.8\;kg/m^2/year$, and a net increase of a river-bed change at a rate of $+5\;cm/m^2$/year in the Kangkyeong area. The change in river-bed is interpreted to have been caused by soil erosion in the downstream of the Keum river basin. In addition river-bed change mainly occurred on the downstream of the confluence where tributaries and the main channel meet. Other possible river-bed change is caused by a removal of fluvial sand aggregates, which might have resulted in a net decrease of exposed area of sediment distribution between 1991 and 1995, while a construction of underwater structures, including a bridge, a reclamation of sand bars for rice fields and dikes, resulted in an increase of the exposed area of river-bed due to sediment accumulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.60-68
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• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.