• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.90.1-90.1
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• 2012

1934년 J. R. Winkler에 의해 처음으로 개발된 pulse current 도금은 연속적인 직류 단속을 이용한 전기도금으로써 종래의 연속적인 직류(direct current) 전기 도금이 가지는 다공성 및 거친 도금 등의 한계를 극복하기 위해 연구되고 있다. 최근 전기 전자 산업의 급속한 발달과 함께 Au, Pd, Rh 등의 귀금속 도금에 있어서 Pulse 도금은 광택, 다공도, 내부 응력, 불순물 및 수소 함유량의 감소와 같은 특성 향상을 가질 수 있으며 기존 DC 전기 도금의 문제점 해결책으로서 많은 연구가 이루어지고 있다. 하지만 현재까지 Pulse 도금의 정확한 기구(mechanism)에 대한 명확한 정립이 되어 있지 않아 모든 도금계에 적용할 수 있는 standard pattern이 없는 실정이다. 본 연구에서는 귀금속 도금 중 Ag pulse 도금에 있어서 Peak current density, duty cycle, time이 Ag 도금의 표면 형상, 두께, 열전도율에 미치는 영향에 대해 연구하였다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2011.05a
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• pp.133-134
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• 2011

전기도금을 이용하여 $TiO_2$ 입자들을 니켈 도금층에 넣은 Ni-$TiO_2$ 복합체를 만들때 pH, 전류형태에 따른 열적안정성에 대한 영향을 평가하였다. pH 범위는 1, 2, 3.4 였으며, 전류형태는 직류, duty cycle 50%의 펄스를 사용하였다. pH가 낮으면 도금속도는 낮아졌으나 $TiO_2$의 부피분율은 증가하였고, 펄스를 이용하면 도금속도는 증가하였으나 $TiO_2$ 부피분율은 감소하였다. 경도는 pH가 낮으면 상온에서는 낮았으나 고온에서는 상대적으로 경도값이 높았다.

• Proceedings of the Korean Magnestics Society Conference
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• 2005.06a
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• pp.178-179
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• 2005

• 전기의세계
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• v.37 no.1
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• pp.42-54
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• 1988

본 고에서는 화상표시장치로서의 모든 요건을 대부분 만족시키며 제조공정 등이 비교적 용이하고 평면화상표시장치의 대규모 생산에 알맞는 것으로 알려진 직류형 분말 EL을 이용한 표시장치 기술에 대해 논의한다. 서론에 이어 2장에서는 EL의 동작원리 및 동작특성에 대해 설명하고 3장에서는 투명 전극, EL 분말 처리과정 및 분말의 구리 도금 과정등 직류 EL용 재료의 제조방법 및 특성 등에 대해 기술한다. 4장에서 EL 평판제작 및 발광층 형성 과정에 관해 설명하고 이상의 방법으로 제작된 직류구동형 EL 평판의 열화형태 및 이들의 해결책에 대해 5장에 설명한다. 6장에서는 이들 평판표시장치를 구동하기 위한 주변 전자 회로의 집적화 기술에 대해 설명하며 마지막으로 결론 및 앞으로의 연구방향을 7장에 제시한다.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.37-43
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• 2006

Surface roughness and hardness of the electroplated Sn were characterized with variations of electroplating current density and current mode. The Sn electroplated at $5{\sim}50mA/cm^{2}$ exhibited the surface roughness of $2.0{\sim}2.4{\mu}m$. The Sn electroplated with pulse current mode exhibited low surface roughness compared one processed with direct current mode. With surface annealing at $300^{\circ}C$ for 3 sec using halogen lamp, surface roughness of the Sn bump was substantially reduced to $1{\mu}m$. The Sn electroplated at $5{\sim}50mA/cm^{2}$ exhibited the hardness of 10 Hv. Low contact resistances of $33{\sim}17m{\Omega}$ were obtained for specimens flip-chip bonded with Sn bumps.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.63-69
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• 2007

We investigated interconnection processes using Cu vias for MEMS sensor packages. Ag paste layer was formed on a glass substrate and used as a seed layer for electrodeposition of Cu vias after bonding a Si substrate with through-via holes. With applying electrodeposition current densities of $20mA/cm^2\;and\;30mA/cm^2$ at direct current mode to the Ag paste seed-layer, Cu vias of $200{\mu}m$ diameter and $350{\mu}m$ depth were formed successfully without electrodeposition defects. Interconnection processes for MEMS sensor packages could be accomplished with Ti/Cu/Ti line formation, Au pad electrodeposition, Sn solder electrodeposition and reflow process on the Si substrate where Cu vias were formed by Cu electrodeposition into through-via holes.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.71-76
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• 2008

The mechanical properties of Ni-Fe alloy were varied with the current type, current density and bath conditions such as concentrations and temperature. The effect of electroplating parameters on the surface hardness, mechanical strength, residual stress and wear properties were investigated. The mechanical properties of electrodeposits with PC plating is superior to those with DC plating. Ni-Fe electrodeposits with PC has approximately 50% lower residual stress than that of DC plating. The tensile strength of PC electroplated specimen was 15% higher than that of DC electroplated specimen. The wear resistance of PC specimen was 30% improved relative to that of DC specimen.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.117-123
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• 2014

Cu through-vias, which can be used as thermal vias or vertical interconnects, were formed using bottom-up electrodeposition filling as well as top-down electrodeposition filling into open via-holes and their microstructures were observed. Solid Cu through-vias without voids could be successfully formed by bottom-up filling as well as top-down filling with direct-current electrodeposition. While chemical-mechanical polishing (CMP) to remove the overplated Cu layer was needed on both top and bottom surfaces of the specimen processed by top-down filling method, the bottomup process has an advantage that such CMP was necessary only on the top surface of the sample.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.129-134
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• 2005

Electroplating copper is the important role in formation of 3D stacking interconnection in SiP (System in Package). The I-V characteristics curves are investigated at different electrolyte conditions. Inhibitor and accelerator are used simultaneously to investigate the effects of additives. Three different sizes of via are tested. All via were prepared with RIE (reactive ion etching) method. Via's diameter are 50, 75, $100{\mu}m$ and the height is $100{\mu}m$. Inside via, Ta was deposited for diffusion barrier and Cu was deposited fer seed layer using magnetron sputtering method. DC, pulse and pulse revere current are used in this study. With DC, via cannot be filled without defects. Pulse plating can improve the filling patterns however it cannot completely filled copper without defects. Via was filled completely without defects using pulse-reverse electroplating method.

• Transactions of the Korean hydrogen and new energy society
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• v.20 no.2
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• pp.116-124
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• 2009

We investigated the influences of cobalt coating deposited by DC electroplating on the ferritic stainless steel, STS 430, as a protective layer on a metallic interconnect for SOFC applications. Cobalt coated STS 430 revealed a uniform and denser-packing oxide surface and a reduced growth rate of $Cr_2O_3$ scales after oxidation at $800^{\circ}C$in air. Cobalt coating layer was oxidized to $CoCo_2O_4$ and Co containing mixed oxide spinels such as $Co_2CrO_4$, $CoCr_2O_4$, and $CoCrFeO_4$. The area specific resistance value of Co coated sample was $0.020\;{\Omega}cm^2$ lower than that of uncoated at $800^{\circ}C$ in air during 500 h. After 1000 h oxidation, cobalt oxide coating layer suppressed chromium outward diffusion.