• Title/Summary/Keyword: 지우기 전류

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Electrical Characteristics Analysis of Resistive Memory using Oxygen Vacancy in V2O5 Thin Film (산소공공을 이용한 V2O5 저항성 메모리의 전기적인 동작특성 해석)

  • Oh, Teresa
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.10
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    • pp.1827-1832
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    • 2017
  • To observe the characteristics to be a resistive memory of $V_2O_5$ deposited by oxygen various gas flows and annealed, the hysteresis curves of $V_2O_5$ were analyzed. The good resistive memory was obtained from the electrical characteristics of $V_2O_5$ films with the Schottky contact as a result of electron-hole pair, and the oxygen vacancy generated from the annealing process contributes the high quality of Schottky contact and the formation of resistive memories. The balanced Schottky contacts owing to the oxygen vacancy effect as the result of an ionic reaction were formed at the $V_2O_5$ film annealed at $150^{\circ}C$ and $200^{\circ}C$ and the balanced Schottky contact with negative to positive voltages enhanced the electrical operation with write/erase states according to the forward or reverse bias voltages for the resistive memory behavior due to the oxygen vacancy.

A design on low-power and small-area EEPROM for UHF RFID tag chips (UHF RFID 태그 칩용 저전력, 저면적 비동기식 EEPROM 설계)

  • Baek, Seung-Myun;Lee, Jae-Hyung;Song, Sung-Young;Kim, Jong-Hee;Park, Mu-Hun;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.12
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    • pp.2366-2373
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    • 2007
  • In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.