• Title/Summary/Keyword: 지연 에러

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Performance Analysis of Error Control Techniques Using Forward Error Correction in B-ISDN (B-ISDN에서 Forward Error Correction을 이용한 오류제어 기법의 성능분석)

  • 임효택
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.9A
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    • pp.1372-1382
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    • 1999
  • The major source of errors in high-speed networks such as Broadband ISDN(B-lSDN) is buffer overflow during congested conditions. These congestion errors are the dominant sources of errors in 1high-speed networks and result in cell losses. Conventional communication protocols use error detection and retransmission to deal with lost packets and transmission errors. However, these conventional ARQ(Automatic Repeat Request) methods are not suitable for the high-speed networks since the transmission delay due to retransmissions becomes significantly large. As an alternative, we have presented a method to recover consecutive cell losses using forward error correction(FEC) in ATM(Asynchronous Transfer Mode)networks to reduce the problem. The performance estimation based on the cell discard process model has showed our method can reduce the cell loss rate substantially. Also, the performance estimations in ATM networks by interleaving and IP multicast service are discussed.

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A Study on DCT Hierarchical LMS DFE Algorithm to Improve the Performance of ATSC Digital TV Broadcasting (ATSC 디지털 TV 방송수신 성능개선을 위한 DCT 계층적 LMS DFE 알고리즘 연구)

  • 김재욱;서종수
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.7A
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    • pp.529-536
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    • 2003
  • In this Paper, a new DCT HLMS DFE(Discrete Cosine Transform Hierarchical Least Mean Square Decision Feedback Equalizer) algorithm is proposed to improve the convergence speed and MSE(Mean Square Error) performance of a receive channel equalizer in ATSC(Advanced Television System Committee) 8VSB(Vestigial Side Band) digital terrestrial TV system. The proposed algorithm reduces the eigenvalue range of input data autocorrelation by transforming LMS (Least Mean Square) DFE into the subfilter of hierarchical structure. Moreover, the use of DCT and power estimation algorithm makes it possible to reduce the eigenvalue deviation of input data which results from distortion and delay of the receive signal in the miulti-path environment. Simulation results show that proposed DCT HLMS DFE has SNR improvement of approximately 3.8dB, 5dB and 2dB as compared to LMS DFE when the equalized symbol error rate is 0.2 in ATTC defined digital terrestrial TV broadcasting channels A, B and F, respectively.

A New Congestion Control Algorithm for Vehicle to Vehicle Safety Communications (차량 안전 통신을 위한 새로운 혼잡 제어 알고리즘 제안)

  • Yi, Wonjae
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.18 no.5
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    • pp.125-132
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    • 2017
  • Vehicular safety service reduces traffic accidents and traffic congestion by informing drivers in advance of threats that may occur while driving using vehicle-to-vehicle (V2V) communications in a wireless environment. For vehicle safety services, every vehicle must broadcasts a Basic Safety Message(BSM) periodically. In congested traffic areas, however, network congestion can easily happen, reduce the message delivery ratio, increase end-to-end delay and destabilize vehicular safety service system. In this paper, to solve the network congestion problem in vehicle safety communications, we approximate the relationship between channel busy ratio and the number of vehicles and use it to estimate the total network congestion. We propose a new context-aware transmit power control algorithm which controls the transmission power based on total network congestion. The performance of the proposed algorithm is evaluated using Qualnet, a network simulator. As a result, the estimation of total network congestion is accurately approximated except in specific scenarios, and the packet error rate in vehicle safety communication is reduced through transmit power control.

A Study On The Wireless ATM MAC Protocol Using Mini-slot With Dynamic Bandwidth Allocation Algorithm (동적 대역 할당 알고리즘을 이용한 미니슬롯 기반의 무선 ATM 매체 접속 제어 프로토콜에 관한 연구)

  • Jeong, Geon-Jin;Lee, Seong-Chang
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.37 no.2
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    • pp.17-23
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    • 2000
  • Wireless link has high bit error rate compared with wired link and many users share this limited bandwidth. So it needs more powerful error control code and efficient media access control(MAC) to provide multimedia service reliably. In this paper we proposed efficient MAC frame format based on TDMA using mini-slot for request access. The number of mini-slots is variable based on the result of collision in the previous frame. This dynamic allocation of request mini-slots helps resolve the contention situation quickly and avoids the waste of bandwidth that may occur when there are several unneeded request mini-slots. The simulation results are also presented in terms of channel utilization, call blocking probability and cell transmission delay for mixed traffic environment.

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Position Synchronization Control of Single Link Manipulators (단일 링크 머니퓰레이터들에 대한 위치 동기화 제어)

  • Song, Ki-Won
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.48 no.3
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    • pp.6-12
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    • 2011
  • Electric vehicles and robots are real-time distributed control systems composed of multiple drive subsystems using micro controller units. Each control subsystem should be modular, compact, power saving, interoperable and fault tolerable in order to be incorporated into the networked real-time distributed control system. Under the networked real-time distributed control the synchronization problem can be occurred to the position and orientation tracking control due to the load variance, mismatch and time delay between the multiple drive subsystems. This paper suggests two types of position synchronization control of the single link manipulators. One of them is composed of cross controller, Kalman filter and disturbance observer, and the other uses the generation of target trajectories to minimize the gradient vector of the scalar function which is composed of the sum of square errors between the reference input vector and the output vectors. The availability of the proposed control schemes is shown through the control experiments.

Fully-Parallel Architecture for 1.4 Gbps Non-Binary LDPC Codes Decoder (1.4 Gbps 비이진 LDPC 코드 복호기를 위한 Fully-Parallel 아키텍처)

  • Choi, Injun;Kim, Ji-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.4
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    • pp.48-58
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    • 2016
  • This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

A Study on the Next Generation Dedicated Short Range Communication System using OFDM (OFDM 방식의 차세대 단거리전용 통신 시스템 성능 개선에 관한 연구)

  • Kim, Man-Ho;Kang, Heau-Jo
    • Journal of Advanced Navigation Technology
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    • v.10 no.4
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    • pp.394-399
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    • 2006
  • In this paper, we investigated performance for 5.8GHz dedicated short range communication system using OFDM which will be applied to Intelligent transportation system services. The maximum speed of a vehicle in DSRC channel is very fast as 180km/h, so a service time is very short to serve a various traffic information if hand-off is not occurred. Therefore higher bit rate is required to proved advanced and intelligent service to the drivers of various vehicle and the data transmission rate of the next generation DSRC system if being promoted over 10Mbps. The signals received in Clarke & Gans channel have been simulated using the computer simulator.

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Resource Allocation and Transmission Control Scheme using Window-Based Dynamic Bandwidth Smoothing Method (윈도우 기반 동적 대역폭 평활화 방식을 이용한 자원 할당 및 전송 제어 기법)

  • Kim Hyoung-Jin;Go Sung-Hyun;Ra In-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.5
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    • pp.943-950
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    • 2005
  • Recently, many of researches on stream transmission for satisfying each of different real-time transmission condition of the multimedia data that demands various service quality through high-speed networks have been studied actively. In this paper, we design a scheme that discriminately reserves the network resources for the transmission of each multimedia application and propose a bandwidth allocation scheme for improving the utilization ratio of free resources. And we also propose a pipelining scheme for providing flexible real-time transmission. The proposed schemes can be used to support a real-time transmission by applying feedback transmission control method based on receiving buffer for guaranteeing the synchronization conditions requested by the multimedia data. Moreover, we propose a transmission control scheme that can take the amount of network resources down to the minimum amount within the range of permissible error-range under the guarantee with no quality degradation simultaneously when the bottleneck is caused by the network congestion. Finally, we propose a dynamic bandwidth smoothing scheme that can smooth the maximum bandwidth to the demand of each video steam for giving continuous transmission to the delay sensitive video steam between senders and receivers.

Low-Complexity and High-Speed Multi-Size Circular Shifter With Benes Network Control Signal Optimization for WiMAX QC-LDPC Decoder (Benes 네트워크 제어 신호 최적화를 이용한 WiMAX QC-LDPC 복호기용 저면적/고속 Multi-Size Circular Shifter)

  • Kang, Hyeong-Ju
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.10
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    • pp.2367-2372
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    • 2015
  • One of various low-density parity-check(LDPC) codes that has been adopted in many communication standards due to its error correction ability is a quasi-cyclic LDPC(QC-LDPC) code, which leads to comparable decoder complexity. One of the main blocks in the QC-LCDC code decoder is a multi-size circular shifter(MSCS) that can perform various size rotation. The MSCS can be implemented with many structures, one of which is based on Banes network. The Benes network structure can perform the normal MSCS operation efficiently, but it cannot use the properties coming from specifications like rotation sizes. This paper proposesd a scheme where the Benes network structure can use the rotation size property with the modification of the control signal generation. The proposed scheme is applied to the MSCS of IEEE 802.16e WiMAX QC-LDPC decoder to reduce the number of MUXes and the critical path delay.

Design and Evaluation of a Fast Boot-up Technique for Flash Memory based Computer Systems (플래시메모리 기반 컴퓨터시스템을 위한 고속 부팅 기법의 설계 및 성능평가)

  • Yim, Keun-Soo;Kim, Ji-Hong;Koh, Kern
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.11_12
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    • pp.587-597
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    • 2005
  • Flash memory based embedded computing systems are becoming increasingly prevalent.These systems typically have to provide an instant start-up time. However, we observe that mounting a file system toy flash memory takes 1 to 25 seconds mainly depending on the flash capacity. Since the flash chip capacity is doubled in every year, this mounting time will soon become the most dominant reason of the delay of system start-up time Therefore, in this paper, we present instant mounting techniques for flash file systems by storing the In-memory file system metadata to flash memory when unmounting the file system and reloading the stored metadata quickly when mounting the file system. These metadata snapshot techniques are specifically developed for NOR- and NAND-type flash memories, while at the same time, overcoming their physical constraints. The proposed techniques check the validity of the stored snapshot and use the proposed fast trash recovery techniques when the snapshot is Invalid. Based on the experimental results, the proposed techniques can reduce the flash mounting time by about two orders of magnitude over the existing de facto standard flash file system, JFFS2.