• The Journal of the Korea Contents Association
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• v.21 no.7
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• pp.164-170
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• 2021

In VLSI design, partitioning is a task of clustering objects into groups so that a given objective circuit is optimized. It is used at the layout level to find strongly connected components that can be placed together in order to minimize the layout area and propagation delay. The most popular algorithms for partitioning include the Kernighan-Lin algorithm, Fiduccia-Mattheyses heuristic and simulated annealing. In this paper, we propose a adapted genetic algorithm searching solution space for the circuit partitioning problem, and then compare it with simulated annealing and genetic algorithm by analyzing the results of implementation. As a result, it was found that an adaptive genetic algorithm approaches the optimal solution more effectively than the simulated annealing and genetic algorithm.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.6
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• pp.44-52
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• 2017

In this paper, we propose a DFD (Digital Frequency Discriminator) design that has better frequency discrimination and a smaller size. Electronic warfare equipment can analyze different types of radar signal such as those based on Frequency, Pulse Width, Time Of Arrival, Pulse Amplitude, Angle Of Arrival and Modulation On Pulse. In order for electronic warfare equipment to analyze radar signals with a narrow pulse width (less than 100ns), they need to have a special receiver structure called IFM (Instantaneous Frequency Measurement). The DFD (Digital Frequency Discriminator) is usually used for the IFM. Because the existing DFDs are composed of separate circuit devices, they are bulky, heavy, and expensive. To remedy these shortcomings, we use a three delay line ($1{\lambda}$, $4{\lambda}$, $16{\lambda}$) in the DFD, instead of the four delay line ($1{\lambda}$, $4{\lambda}$, $16{\lambda}$, $64{\lambda}$) generally used in the existing DFDs, and apply the microwave integrated circuit method. To enhance the frequency discrimination, we detect the pulse amplitude and perform temperature correction. The proposed DFD has a frequency discrimination error of less than 1.5MHz, affording it better performance than imported DFDs.

• The Journal of the Acoustical Society of Korea
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• v.38 no.4
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• pp.450-458
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• 2019

Passive cavitation imaging method is used to observe the ultrasonic waves generated when a group of bubbles collapses. A problem with passive cavitation imaging is a low resolution and large side lobe levels. Since ultrasound signals generated by passive cavitation take the form of a pulse, the amplitude distribution of signals received across the receive channels varies depending on the direction of incidence. Both the centroid and flatness were calculated to determine weights at imaging points in order to discriminate between the main and side lobe signals from the signal amplitude distribution of the received channel data and to reduce the side lobe levels. The centroid quantifies how the channel data are distributed across the receive channel, and the flatness measures the variance of the channel data. We applied the centroid weight and the flatness to the passive cavitation image constructed using the delay-and-sum focusing and minimum variance beamforming methods to improve the image quality. Using computer simulation and experiment, we show that the application of weighting in delay-and-sum and minimum variance beamforming reduces side lobe levels.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.36-43
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• 2006

In this paper we present a new high-speed parallel multiplier for Performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the MOD operation part to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of MOD operation part have two AND gates and two XOR gates. Using these MOD operation parts, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the MOD operation parts with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI. Also, since this circuit has a low propagation delay time generated by the gates during operating process because of not use the memory elements in the inside of multiplier circuit, this multiplier circuit realizes a high-speed operation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.1
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• pp.28-35
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• 2010

In this paper, we designed and fabricated a ultra-wideband(UWB) bandpass filter with a good performance of a stopband, and a notched band in passband. The transformed equivalent circuit of the highpass filter was realized by distributed element. A wide-passband with 3-dB fractional bandwidth of more than 100 % was achieved by using optimum response of the HPF. For improving lower and upper stopband characteristic, a cross coupling between feed lines was employed, which was analyzed by desegmentation technique. In order to reject interference of Wireless LAN and Hyper LAN(5.15~5.825 GHz), the narrow notched(rejection) band was realized by a spurline. The fabricated BPF indicated the passband from 3.1 to 10.55 GHz and the flat group delay of less than 0.94 ns over the entire passband except the rejection band. The filter shown sharp attenuation both inside and outside the band and notched band from 5.2 to 6.12 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.126-135
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• 2007

This paper proposes a new miniaturization method for a parallel coupled line filter with enhanced bandwidth characteristics. A previous method incorporated several advantages, such as size reduction through the use of only a small number of capacitors, in addition to grounding, suppression of harmonic characteristics, and improved skirt characteristics for the parallel coupled line filter, which is conventional in the field of RE filters due to its design and fabrication simplicity. However, the previous method also has disadvantages related to the bandwidth shrinkage of the miniaturized filters. In this paper, the amount of bandwidth shrinkage is analyzed in terms of the relationship between the loaded Q(quality factor) and the group delay of a resonator. Moreover, the reduction in the bandwidth is solved by a design with new design equations. To show the validity of the proposed method, a hairpin filter with a center frequency of 5.2 GHz and an fractional bandwidth(FBW) of 10% was scaled down to half its original dimension by the proposed method with the enhanced bandwidth characteristics. The measured result shows a high level of agreement with theoretical results.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.224-234
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• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that if fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs bu 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.79-85
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• 2001

In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.

• Journal of the Korean Vacuum Society
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• v.17 no.6
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• pp.518-522
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• 2008

The miniaturization of device size and multilevel interlayers have been developed by ULSI circuit devices. These submicron processes cause serious problems in conventional metallization due to the solubility of silicon and metal at the interface, such as an increasing contact resistance in the contact hole and interdiffusion between metal and silicon. Therefore it is necessary to implement a barrier layer between Si and metal. Thus, the size of multilevel interconnection of ULSI devices is critical metallization schemes, and it is necessary reduce the RC time delay for device speed performance. So it is tendency to study the Cu metallization for interconnect of semiconductor processes. However, at the submicron process the interaction between Si and Cu is so strong and detrimental to the electrical performance of Si even at temperatures below $200^{\circ}C$. Thus, we suggest the tungsten-carbon-nitrogen (W-C-N) thin film for Cu diffusion barrier characterized by nano scale indentation system. Nano-indentation system was proposed as an in-situ and nanometer-order local stress analysis technique.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.6
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• pp.467-478
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• 2019

This paper describes the development and measurement results of a wide-band planar active phase array antenna system for an electronic warfare jamming transmitter. The system is designed as an $8{\times}8$ triangular lattice array using a $45^{\circ}$ slant wide-band antenna. The 64-element transmission channel is composed of a wide-band gallium nitride(GaN) solid state power amplifier and a gallium arsenide(GaAs) multi-function core chip(MFC). Each GaAs MFC includes a true-time delay circuit to avoid a wide-band beam squint, a digital attenuator, and a GaAs drive amplifier to electronically steer the transmitted beam over a ${\pm}45^{\circ}$ azimuth angle and ${\pm}25^{\circ}$ elevation angle scan. Measurement of the transmitted beam pattern is conducted using a near-field measurement facility. The EIRP of the designed system, which is 9.8 dB more than the target EIRP performance(P), and the ${\pm}45^{\circ}$ azimuth and ${\pm}25^{\circ}$ elevation beam steering fulfill the desired specifications.