• Title/Summary/Keyword: 지연 라인 컨트롤러

Search Result 2, Processing Time 0.021 seconds

Development of Improved String Model for Instruments with Anjok (안족이 있는 악기의 개선된 현의 모델 개발)

  • Cho, Sang-Jin;Chong, Ui-Pil
    • The Journal of the Acoustical Society of Korea
    • /
    • v.26 no.7
    • /
    • pp.328-333
    • /
    • 2007
  • In this paper, we describe characteristics of a movable bridge called the Anjok and propose an improved string model which has delay line controller in physical modeling of the Gayageum. Movable bridge, the Anjok determines the length of vibrating string and transmits the vibration of each string to the body of the Gayageum. We analyze the variations in frequency domain and implement the Anjok model as parametric form using the first-order polynomial fitting in logarithmic scale graph, because the length of string changes fundamental frequency. In order to implement the Anjok model, frequency fitting, tension fitting and frequency fitting using leaky integrator are used. The frequency fitting using leaky integrator has the best results among those. Proposed string model with the Anjok model can represent real tuning system of the real Gayageum and the proposed model could synthesize sounds which is similar to original sounds.

Image Cache for FPGA-based Real-time Image Warping (FPGA 기반 실시간 영상 워핑을 위한 영상 캐시)

  • Choi, Yong Joon;Ryoo, Jung Rae
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.53 no.6
    • /
    • pp.91-100
    • /
    • 2016
  • In FPGA-based real-time image warping systems, image caches are utilized for fast readout of image pixel data and reduction of memory access rate. However, a cache algorithm for a general computer system is not suitable for real-time performance because of time delays from cache misses and on-line computation complexity. In this paper, a simple image cache algorithm is presented for a FPGA-based real-time image warping system. Considering that pixel data access sequence is determined from the 2D coordinate transformation and repeated identically at every image frame, a cache load sequence is off-line programmed to guarantee no cache miss condition, and reduced on-line computation results in a simple cache controller. An overall system structure using a FPGA is presented, and experimental results are provided to show accuracy and validity of the proposed cache algorithm.