• Journal of the Institute of Convergence Signal Processing
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• v.6 no.4
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• pp.206-211
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• 2005

We describe the design for a correlator and an access code generator in bluetooth system. These are used for a connection setting, a packet decision and a clock synchronization between Bluetooth units. The correlator consists of two blocks; carry save adder based on Wallace tree and threshold-value decision block. It determines on an useful packet and clock-synchronization for input signal of 1.0Mbps through the sliding-window correlating. The access-code generator also consists of two blocks; BCH(Bose-Chadhuri-Hocquenghem) cyclic encoder and control block. It generates the access-codes according to four steps' generation process based on Bluetooth standard. In order to solve synchronization problem, we make use of any memory as a pseudo random sequence. The proposed correlator and access-code generator were coded with VHDL. An FPGA Implementation of these modules and the simulation results are proved by Xilinx chip. The critical delay and correlative margin based on synthesis show the 4.689ns and the allowable correlation-error up to 7-bit.

• Aerospace Engineering and Technology
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• v.3 no.1
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• pp.170-178
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• 2004

This paper deals with six degree-of-freedom HILS(hardware-in-the-loop-simulation) of KSR-III rocket using a TAFMS(three axis flight motion simulator). This TAFMS HILS test is accomplished before main HILS tests in order to verify the control stability in the presence of TAFMS dynamic effects. The TAFMS HILS test includes initial attitude holding tests for INS initial alignment procedures, timer synchronization tests with an auxiliary lift-off signal, real-time calibration tests using an external thermal recorder, open-loop TAFMS operating tests, and final closed-loop TAFMS HILS tests using the TAFMS attitude measurements as inputs to the closed control loop. The HILS tests are accomplished for several flight conditions composed with nominal flight condition, TWD effect added condition, slosh modes and/or bending modes existing condition, and windy condition, etc.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.398-405
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• 2005

The multiuser detection (MUD) based wireless receiver requires more accurate channel estimation than the single user detection (SUD) schemes such as Rake receiver, and hence the post processing is required for MUD to clean up the estimated channel coefficients by eliminating the noise only coefficients. The adaptive post processing method is proposed in order to provide more accurate channel responses and the power level of the background noise and interferences at the cost of the negligible processing delay compared to the conventional method based on the threshold test with the threshold value relative to the noise variance. The simulations are performed in 3GPP-TDD mode environment. The results show that the noise estimation error of the proposed method is maximum $10\%$, which is much smaller than $50\%$ maximum error of the conventional method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12A
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• pp.1311-1319
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• 2007

This paper presents the VHDL implementation procedure of the passive RFID tag operating in Ultra High Frequency. The operation of the tag compatible with the EPCglobal Class1 Generation2(GEN2) protocol is verified by timing simulation after synthesis and implementation. Due to the reading range with relatively large distance, a passive tag needs digital processor which facilitates faster decoding, encoding and state transition for enhancement of an interrogation rate. In order to satisfy linking time, the pipe-line structure is used, which can minimize latency to serial input data stream. We also propose the sampling strategy to decode the Preamble, the Frame-sync and PIE symbols in reader commands. The simulation results with the fastest data rate and multi tags environment scenario show that the VHDL implemented tag performs faster operation than GEN2 proposed.

• Journal of the Korea Society for Simulation
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• v.16 no.3
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• pp.57-63
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• 2007

In real time rendering of fetus the empty space leaping while traversing a ray is most frequently used accelerating technique. The main idea is to skip empty voxel samples which do not contribute the result image and it speeds up the rendering time by avoiding sampling data while traversing a ray in the empty region, saving a substantial number of interpolations. Calculating the distance from the nearest object boundary for every yokel can reduce the sampling operation. Among widely-well-known distance maps, those estimates the true distance, such as euclidean distance, takes a long time to compute because of the complicated floating-point operations, and others which uses approximated distance functions, such as city-block and chessboard, provides faster computation time but sampling error may can occur. In this paper, therefore, we analyze the characteristics of several distance maps and compare the number of samples and rendering time. And we aim to suggest the most appropriate distance map for rendering of fetus in ultrasound image.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.2
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• pp.142-152
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• 1992

This paper presentes a new method to measure high electric field (or high voltage) by using crystalline SiO2 which has very high half wave voltage. There are many difficulties in measuring high electric field using other crystals which have generally low half wave voltage.By applying Stokes parameter and Mueller matrix. We derive optical modulation equation in the sensor which is composed of a polarizer, and Mueller matrix, we derive optical modulation equation in the sensor which is composed of a polarizer, a Pokels material, and an analyzer, We theoretically analyzed electro-optic effect, and calculated the phase retardation and half wave volt age of the birefringent material. The designed optical valtage sensor has very excellent linearity up to 20KV without divided volt-age. The maximum error was measured within 3%. Before annealing of Sio2 crystal, the maximum variation of the output voltage is 7.5% with varying temperature from \ulcorner20˚c to 60˚c. But, after annealing of SiO2 crystal, the output voltage variation is improved within 1%error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.6C
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• pp.483-491
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• 2012

In vehicle-to-vehicle (V2V) communications, each vehicle should periodically disseminate a beacon message including the kinematics information, such as position, speed, steering, etc., so that a neighbor vehicle can better perceive and predict the movement of the vehicle. However, a simple broadcasting of such messages may lead to a low reception probability as well as an excessive delay. In this paper, we attempt to analyze the impact of the following key parameters of the beacon dissemination on the performance of vehicular networks: beacon period, carrier-sensing range, and contention window (CW) size. We first derive a beacon period which is inversely proportional to the vehicle speed. Next, we mathematically formulate the maximum beacon load to demonstrate the necessity of the transmit power control. We finally present an approximate closed-form solution of the optimal CW size that leads to the maximum throughput of beacon messages in vehicular networks.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.51-60
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• 2005

In this paper, we propose an enhanced SIR measurement algorithm for WCDMA mobile station modem. The proposed algorithm minimizes processing delay by applying velocity estimation-based channel estimator with IIR filter and reduces measured SIR offset by compensating attenuated signal power by using pilot channel(CPICH) in fading channel environment. To improve stability of SIR measurement, we also adopt an IIR filter which can properly reflect variation of fading channel in signal and interference power measurement. We prove that the proposed algorithm outperforms conventional SIR measurement algorithm in mean and jitter of measured SIR. Computer simulation shows that performance results using the proposed algorithm have improvement of approximately 8dB for measured mean and 2dB for measured jitter in the wireless mobile channel, especially in fast mobile speed environment.

• Journal of Satellite, Information and Communications
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• v.8 no.2
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• pp.29-35
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• 2013

In this paper, we investigate the type and detection methode of spoofing attack, and then analyze the performance of spoofing detection algorithm in GPS L1 signal through the simulation. Generally spoofer is different from the jammer, because the receiver can be operated and not. In case of spoofing the GPS receiver is hard to recognize the spoofing attack and can be operated normally without stopping because the spoofing signal is the mimic GPS signal. To evaluate the performance of spoofing detection algorithm, both the software based spoofing and GPS signal generator and the software based GPS receiver are implemented. In paper, we can check that spoofing signal can affect to the DLL and PLL tracking loop because code delay and doppler frequency of spoofing. The spoofing detection algorithm has been implemented using the pseudorange, signal strength and navigation solution of GPS receiver and proposed algorithm can effectively detect the spoofing signal.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.408-414
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• 2014

This paper proposes a charge-pump phase-locked loop (PLL) with 51-phase output clock of a 125 MHz target frequency. The proposed PLL uses three voltage controlled oscillators (VCOs) to generate 51-phase clock and increase of maximum operating frequency. The 17 delay-cells consists of each VCO, and a resistor averaging scheme which reduces the phase mismatch among 51-phase clock combines three VCOs. The proposed PLL uses a 65 nm 1-poly 9-metal CMOS process with 1.0 V supply. The simulated peak-to-peak 지터 of output clock is 0.82 ps at an operating frequency of 125 MHz. The differential non-linearity (DNL) and integral non-linearity (INL) of the 51-phase output clock are -0.013/+0.012 LSB and -0.033/+0.041 LSB, respectively. The operating frequency range is 15 to 210 MHz. The area and power consumption of the implemented PLL are $580{\times}160{\mu}m^2$ and 3.48 mW, respectively.