• The KIPS Transactions:PartC
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• v.10C no.1
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• pp.87-94
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• 2003

As the number of the Internet users increases explosively, a solution for this problem is web caching. So, many techniques on improving cache server performance have been suggested. In this paper, we analyze the cause of the bottleneck in cache servers, and propose an arbitral thread and delayed caching mechanism as a solution. We use an arbitral thread in order to provide a quick service to user requests through eliminating the ready multi-thread search problem in case of disk writing operation. We also use delayed caching in order to provide stable system operation through avoiding overloaded disk operation and queue threshold. Proposed cache server is implemented through modification on SQUlD cache server, and we compare its performance with the original SQUID cache server.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.59-70
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• 2004

SMT(Simultaneous Multi Threading) architecture uses TLP(Thread Level Parallelism) and increases processor throughput, such that issue slots can be filled with instructions from multiple independent threads. Having multiple ready threads reduces the probability that a functional unit is left idle, which increases processor efficiency. To utilize those advantages for the SMT processors, the issue unit must control the flow of instructions from different threads and not create conflicts among those instructions, which make the SMT issue logic extremely complex. Therefore, our SMT architecture, which is modeled in this paper, uses an in-order-issue and completion scheme, and therefore, can use a simple issue mechanism with a scoreboard already instead of using register renaming or a reorder buffer. However, an SMT scoreboarding mechanism is still more complex and costlier than that of a single threaded conventional processor. This paper proposes an optimal implementation of a scoreboarding mechanism for an ARM-based SMT architecture.