• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.50-57
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• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.503-510
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• 2006

Readout circuit is to convert signal occurred in a defector into suitable signal for image signal processing. In general, it has to possess functions of impedance matching with perception element, amplification, noise reduction and cell selection. It also should satisfies conditions of low-power, low-noise, linearity, uniformity, dynamic range, excellent frequency-response characteristic, and so on. The technical issues in developing image processing equipment for focal plane way (FPA) can be categorized as follow: First, ultraviolet (UV) my detector material and fine processing technology. Second, ReadOut IC (ROIC) design technology to process electric signal from detector. Last, package technology for hybrid bonding between detector and ROIC. ROIC enables intelligence and multi-function of image equipment. It is a core component for high value added commercialization ultimately. Especially, in development of high-resolution image equipment ROIC, it is necessary that high-integrated and low-power circuit design technology satisfied with design specifications such as detector characteristic, signal dynamic range, readout rate, noise characteristic, ceil pitch, power consumption and so on. In this paper, we implemented a $8\times8$ FPA prototype ROIC for reduction of period and cost. We tested unit block and overall functions of designed $8\times8$ FPA ROIC. Also, we manufactured ROIC control and image boards, and then were able to verify operation of ROIC by confirming detected image from PC's monitor through UART(Universal Asynchronous Receiver Transmitter) communication.

• Proceedings of the Korea Water Resources Association Conference
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• 2011.05a
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• pp.85-85
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• 2011

홍수기에 안전하고 정확한 유량측정을 통하여 물관리에 필요한 기초수문자료를 확보하고자 한국수자원공사에서 1993년도부터 홍수유량측정기술 확보를 위한 연구를 시작하였다. 그간의 연구성과를 바탕으로 1999년도에 하천의 유속을 비접촉식으로 측정할 수 있는 홍수용 전자파표면유속계를 개발하여 특허등록하였고 그와 동시에 이의 상품화를 추진하여 2010년도까지 75대를 보급하여 실무에서 이용하고 있다. 이동식인 홍수용 전자파표면유속계를 바탕으로 2001년도에는 고정식 실시간 홍수유량측정측정시스템을 개발하여 특허등록하였고, 이 시제품을 현재 용담 수자원시험유역의 동향지점에서 시험운영하고 있다. 또한, 현장 유량측정실무자들의 홍수용 전자파표면유속계 개선요구에 따라 편각용 전자파표면유속계 시제품을 개발하였으며, 이는 임의의 한 지점에 설치한 한 대의 장비로 좌우 여러 측선의 유속을 동시에 측정할 수 있는 다점 측정기능을 갖도록 성능을 개선하였다. 이에 따라 홍수시 유량측정에 소요되는 시간이 줄어들어 신속하게 유량측정을 완료할 수 있는 계기를 마련하였다. 이와 더불어 유속측정 범위를 확장하여 홍수시의 고유속 뿐만 아니라 0.5 m/s 이하의 저유속까지 측정할 수 있는 범용 전자파표면유속계의 시제품을 추가로 개발하였다. 이 장비는 최저유속 0.03 m/s의 측정을 실내시험을 통하여 입증하였다. 범용 전자파표면유속계는 상품화 시제품의 개발을 목표로 기존 시제품의 현장시험을 통하여 현장적용상의 문제점에 대한 해결에 주력하였다. 첫째, 평갈수용 전자파표면유속계의 사용편의를 개선하기 위하여 소형화 및 경량화를 추진하였고, 이를 위하여 사용주파수를 기존의 10 GHz에서 24 GHz로 변경함으로써 $35{\times}35\;cm$ 크기의 기존안테나를 $22{\times}22\;cm$ 크기로 소형화하였으며 송수신부의 무게는 기존 18 kg에서 3.3 kg으로 혁신적으로 줄이는데 성공하였다. 이를 위하여 안테나는 기존의 반사형안테나에서 도파관슬롯배열안테나로 변경하였다. 둘째, 측정값의 안정화를 위하여 안테나의 특성을 개선하여 부엽(side-lobe) 레벨 30 dB 이하 그리고 전후방비(front-back ratio) 50 dB 이하로 개선하여 안테나가 지향하는 방향 이외의 위치에서 반사되는 불필요한 신호를 줄였다. 또한 적응형 이득제어(adaptive gain control)기법의 채택으로 미소 신호에 대한 안정적 측정 및 과다 신호에 대한 능동적 감쇄를 할 수 있도록 시스템을 구성하여 전 유속범위에 대한 안정적 측정을 가능토록 설계 및 제작하였다. 셋째, 자가점검 기능을 탑재하여 유속측정 전에 기기의 상태에 대한 self test기능을 통하여 측정자가 기기의 상태를 사전에 파악 가능토록함으로써, 기기 오작동에 대한 능동 대처할 수 있도록 하였다. 이외에도 저전력 회로설계를 통하여 배터리 사용시간을 확장하였고, 기존의 전자파표면유속계가 가지고 있던 방습 및 방수에도 내성을 갖는 제품으로 설계하였으며 스마트기기를 이용한 무선측정 및 세련된 디자인 등 사용자의 요구사항을 충분히 반영하였다.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.2
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• pp.70-75
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• 2014

Recently, the demand for high-integrated, low-powered, and high-powered SoC design has been increasing due to the multi-functionality and the miniaturization of digital devices and the high capacity of service informations. With the rapid evolution of the system, the required hardware performances have become diversified, the FPGA system has been increasingly adopted for the rapid verification, and SoC system using the FPGA and the ARM core for control has been growingly chosen. While the AXI bus is used in these kinds of systems in various ways, it is traditionally designed with AXI slave structure. In slave structure, there are problems with the CPU resources because CPU is continually involved in the data transfer and can't be used in other jobs, and with the decreased transmission efficiency because the time not used of AXI bus beomes longer. In this paper, an efficient AXI master interface is proposed to solve this problem. The simulation results show that the proposed system achieves reductions in the consumption clock by an average of 51.99% and in the slice by 31% and that the maximum operating frequency is increased to 107.84MHz by about 140%.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.35 no.2
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• pp.129-135
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• 1999

The telemetry system for the current speed and direction, the underwater ambient noise and the distribution ecology of fishes was constructed by the author and his collaborator in order to product and manage effectively in shallow sea culture and setnets fisheries, and then the experiments for the telemetry system carried out at set net fishing ground located Nungpobay in Kojedo from October 1996 to June 1997. As this results, the techniques suggested in the telemetry system gave full display its function even though far away 1.5 km from transmitting part, but with the suggested telemetry system could not be ascertained relationship between physical environment and distribution ecology of fishes.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.108-108
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• 2000

급증하는 무선통신 정보수요는 특히, 고주파대역 (300NHz-300GHz)에서 사용되는 공진기, 필터, 발진기 등과 같은 소자의 품질향상을 요구하고 있다. 고주파용 유전체 중 ZrTiO4 는 $\alpha$-PbO2 계열의 사방정구조를 갖고 있는 유전체로서 높은 유전율 ($\varepsilon$=40)과 높은 품질계수 (Q=1/tan$\delta$=4700 at 7GHz)를 갖고 있고, Sn 첨가시 0ppm/$^{\circ}C$의 공진주파수 온도계수를 얻을 수 있다고 보고되어 있다. 본 연구에서는 약 110$0^{\circ}C$ 이상에서 안정한 상으로 존재하는 ZrTiO4를 저온에서 증착하여 준안정한 상태로 결정화되게 한후, 유전손실 (tan$\delta$)과 유전율($\varepsilon$)을 측정하였다. 또한 증착온도와 열처리과정에 따른 박막의 us형 (Strain) 정도의 변화를 X-선 회절결과로부터 분석하였으며 이를 측정된 유전특성 값과 비교하였다. ZrTiO4 박막은 DC magnetron reactive sputter로 Zr과 Ti 타겟으로부터 high phosphorous doped Si (100) 기판위에 증착하였다. 압력은 4mTorr로 유지하고 박막의 화학양론적 조성비를 맞추기 위해 각 타겟에 가해지는 power는 Zr/Ti=500W/650W로 고정하고, 반응가스의 비율을 Ar/O2=17sccm/3.5sccm으로 유지하여 박막내에 인입되는 산소량을 제어하였다. 증착 직후와 열처리 후의 박막특성을 비교하기 위해 증착온도를 상온에서부터 $600^{\circ}C$까지 변호시키고 증착후 각각의 시편을 80$0^{\circ}C$ 산소분위기에서 2시간동안 열처리하여 시편을 준비하였다. 박막의 상형성 여부와 결정성변화는 $ heta$-2$\theta$X-선 회절법을 사용하여 조사하였고, EPMA를 이용하여 박막의 조성을 확인하였다. 유전특성의 측정을 위해 백금 상부전극을 증착한 후, impedance analyzer를 이용하여 100kHz 영역에서의 유전손실을 측정하고, 측정된 정전용량과 박막의 두께로부터 유전율을 계산하였다. ZrTiO4 박막은 증착온도 20$0^{\circ}C$ 이상에서 결정성을 보이기 시작했으며, 열처리 이후에는 상온에서 비정질이었던 시편이 $650^{\circ}C$ 이상의 온도에서 결정화되기 시작하였다. 증착온도에 따라 유전손실은 0.038에서 0.017 정도로 감소하는 경향을 나타냈으며, 각각 열처리에 의해서 0.034, 0.005 정도로 다시 감소하였다. 박막의 유전율은 약 35 정도의 값을 나타내었으며 X-선 회절 data로부터 분석한 박막의 변형은 증온도에 따라 7.2%에서 0.04%로 감소하였고 이 이경향은 유전손실은 감소경향과 일치하였다.

• Journal of Internet Computing and Services
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• v.18 no.5
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• pp.17-22
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• 2017

In a MPC coding using excitation source of voiced and unvoiced, it would be a distortion of speech waveform. This is caused by normalization of synthesis speech waveform of voiced in the process of restoration the multi-pulses of representation section. This paper present PCFBD-MPC( Position Compensation Frequency Band Division-Multi Pulse Coding ) used V/UV/S( Voiced / Unvoiced / Silence ) switching, position compensation in a multi-pulses each pitch interval and Unvoiced approximate-synthesis by using specific frequency in order to reduce distortion of synthesis waveform. Also, I was implemented that the PCFBD-MPC( Position Compensation Frequency Band Division-Multi Pulse Coding ) system and evaluate the SNRseg of PCFBD-MPC in coding condition of 8kbps. As a result, SNRseg of PCFBD-MPC was 13.4dB for female voice and 13.8dB for male voice respectively. In the future, I will study the evaluation of the sound quality of 8kbps speech coding method that simultaneously compensation the amplitude and position of multi-pulse source. These methods are expected to be applied to a method of speech coding using sound source in a low bit rate such as a cellular phone or a smart phone.

• Smart Media Journal
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• v.9 no.2
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• pp.16-21
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• 2020

Recently, mobile traffic is increasing exponentially as major traffic is transferred to IoT and visual media data in the dissemination of mobile communication terminals and contents use. In order to overcome the limitations of the existing LTE system, 5G mobile communication technology (5G) is a technology that meets 1000 times data traffic capacity, 4G LTE system acceptance, low latency, high energy efficiency, and high cost compared to 4G LTE system. The path loss due to the use of the frequency domain is very high, so it may be difficult to provide a service compared to the existing 4G LTE system. To overcome these shortcomings, various techniques are under study. In this paper, small cell technology is introduced to improve the system performance of 5G mobile communication systems. The performance is analyzed by comparing the results of small cell technology application, macro communication and small cell communication, and the results of the proposed algorithm application for power control. The analysis results show that the use of small cell technology in the 5th generation mobile communication system can significantly reduce the shadow area and reduce the millimeter wave path loss problem.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.