• Journal of IKEEE
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• v.18 no.1
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• pp.119-127
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• 2014

This paper presents a CMOS readout circuit for MEMS(Micro Electro Mechanical System) acceleration sensors. It consists of a MEMS accelerometer, a capacitance to voltage converter(CVC) and a second-order switched-capacitor ${\Sigma}{\Delta}$ modulator. Correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques are used in the CVC and ${\Sigma}{\Delta}$ modulator to reduce the low-frequency noise and DC offset. The sensitivity of the designed CVC is 150mV/g and its non-linearity is 0.15%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 10% when the input voltage amplitude increases by 100mV, and the modulator's non-linearity is 0.45%. The total sensitivity is 150mV/g and the power consumption is 5.6mW. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V and a operating frequency of 2MHz. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.2
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• pp.202-207
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• 2010

In this paper, a novel voltage-controlled oscillator(VCO) using the open loop multiple split ring resonator(OLMSRR) is presented for improving the phase noise, implemented in 130 nm CMOS technology. Compared with the conventional CMOS LC resonator, the proposed CMOS OLMSRR has the larger coupling coefficient value, which makes a higher Q-factor, and has improved the phase noise of the VCO. The proposed CMOS VCO based OLMSRR has the phase noise of -99.67 dBc/Hz @ 1 MHz in the oscillation frequency. Compared with the VCO using the conventional CMOS LC resonator and the proposed VCO using the CMOS OLMSRR structure has been improved in 7 dB. The prototype 24 GHz CMOS VCO is implemented in 130 nm CMOS and occupies a compact die area of $0.7\;mm{\times}0.9\;mm$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6A
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• pp.488-498
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• 2005

The DAB(Digital Audio Broadcasting) service which is based on the Eureka-147 of Europe is developed to DMB(Digital Multimedia Broadcasting) service that is divided into Terrestrial DMB and Satellite DMB. The Satellite DMB is a new broadcasting service, which will service multi-channel multimedia broadcasting by the portable receiver or the vehicle receiver. In this paper, we consider that link level performance of satellite DMB system A which is based on the COFDM(Coded Orthogonal Division Multiplexing). It uses the OFDM method which is sensitive to nonlinearity, so we analyze the effect of the HPA(High Power Amplifier) nonlinearity. And then we define the appropriate back-off value by performing the link level simulation considering back-off effect. Also we consider the effect of frequency and time offset, and then confirm the overall link level performance by analyzing and verifying a suitable synchronization method for satellite DMB system A.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.7C
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• pp.735-742
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• 2006

In this paper, we explain the operation scheme and fixed-point design method of DFE (Digital Front End), which performs DC offset compensation, automatic frequency control, and automatic gain control over the input signal to the UE (User Equipment) receiver of IEEE 802.16e OFDMA-TDD system. Then, we analyze the performance of DFE under ITU-R M. 1225 Veh-A 60km/h channel environment. To optimize the fixed-point design of DFE, we reduce the number of bit resulted from calculation without performance degradation, leading to the decreased complexity of the operation in H/W, and design the Loop filter with considering trade-off between the Acquisition time and the Stability.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.87-95
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• 2014

This paper describes a dual channel receiver design for CIS interfaces. Each channel includes CTLE(Continuous Time Linear Equalizer), sampler, deserializer and clocking circuit. The clocking circuit is composed of PLL, PI and CDR. Fast lock acquisition time, short latency and better jitter tolerance are achieved by adding OSPD(Over Sampling Phase Detector) and FSM(Finite State Machine) to PI-based CDR. The CTLE removes ISI caused by channel with -6 dB attenuation and the lock acquisition time of the CDR is below 1 baud period in frequency offset under 8000ppm. The voltage margin is 368 mV and the timing margin is 0.93 UI in eye diagram using 65 nm CMOS technology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.1
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• pp.99-108
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• 1999

In this paper, we propose $\pi$/4 QPSK scheme with block modulation algorithm, which can reduce preamble in order to transmit ATM cell efficiently in the uplink channel of LMDS, and also designed a new carrier recovery circuit which can improve carrier synchronization performance of block demodulation algorithm. The $\pi$/4 QPSK scheme employing the proposed block modulation algorithm achieved efficient frame transmission by making use of a few preamble when carrier synchronization, symbol timing synchronization and slot timing synchronization were performed by burst data of ATM cell in LMDS environment. For performance evaluation of the proposed method, a simulation analyzing the variation of carrier synchronization, symbol timing synchronization and slot timing synchronization using LMDS environment and burst mode condition was executed. In the simulation, the proposed method showed a good performance even though the reduced preamble as a few aspossible when carrier synchronization, symbol timing synchronization and slot timing synchronization is performed.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.1
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• pp.7-12
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• 2011

This paper proposes a differential Colpitts-VCO circuit suitable for low phase noise oscillation at the sub-1V supply voltage. Oscillation with low phase noise at the sub-1V supply voltage is facilitated by employing inductors as the current sources of the proposed circuit. One of the two feedback capacitors of the single-ended Colpitts oscillator in the proposed circuit is replaced with the MOS varactor in order to further reduce the resonator loss. Post-layout simulation results using a $0.18{\mu}m$ RF CMOS technology show that the phase noises at the 1MHz offset frequency of the proposed circuit oscillating at the sub-1V supply voltages of 0.6 to 0.9 V are at least 7 dBc/Hz lower than those of the well-known cross-coupled differential VCO.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.67-74
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• 2016

This paper presents a novel multiple orthogonal subcarrier modulation based UHF band RFID communication system. In tag-to-reader communication, the demonstration system can deliver 1.6 Mbps through four subcarriers. To improve data rate while suppressing increase in circuit complexity, tag employs square-waves as the subcarriers and uses individual load modulators for each subcarrier. By using multiple orthogonal subcarrier based modulation, proposed communication system can be operated under existing UHF band RFID regulation. In reader, an OFDM demodulator is used. Since the tag backscatters the reader's CW carrier, carrier frequency offset compensation is not necessary in reader demodulator. Experimental results show that the demonstration system achieves a bit error rate of 10-5 at an Eb/N0 of 10.8 dB.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.1
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• pp.1-6
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• 2014

Recently, orthogonal frequency-division multiplexing(OFDM), with clusters of subcarriers allocated to different subscribers(often referred to as OFDMA), has gained much attention for its ability in enabling multiple-access wireless multimedia communications. In such systems, carrier frequency offsets (CFOs) can destroy the orthogonality among subcarriers. And the mismatch in sampling frequencies between transmitter and receiver can lead to serious degradation due to the loss of orthogonality between the subcarriers. As a result, multiuser interference (MUI) along with significant performance degradation can be induced. In this paper, we present a scheme to compensate for the SFOs and CFOs at the base station of an OFDMA system. A novel sampling frequency offset estimation algorithm is proposed, which is based on the repetition of a symbol at the communication start-up. Then, circular convolutions are employed to generate the interference after the discrete Fourier transform processing, which is then removed from the original received signal to increase the signal to interference power ratio(SIR). Simulation result shows that the proposed scheme can improve system performance.