• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.880-883
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• 2002

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFFT after the getting the frequency, response of deducted channel from channel deductor of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of $\pm$1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.122-133
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• 2013

An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input-to-output delay than the previously reported PDC. Proposed PDC is realized using 130-nm CMOS process and demonstrated by transistor-level simulations. A 5-bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic-lock-free and small-phase-offset delay-locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12A
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• pp.1161-1167
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• 2005

In this Paper, a concept of virtual smart antenna (SA) is introduced for orthogonal Sequency division multiplexing (OFDM)-based cellular systems with a frequency reuse factor equal to 1. The OFDM-based cellular system is robust to multipath channels but has a disadvantage that the intercell interference (ICI) caused by adjacent base stations is large at the edge of a cell. In this paper, after deriving the symbol timing offset estimation scheme for the OFDM signal received from multiple base stations in a quasi-static fading channel, the ICI cancellation method based on virtual smart antenna is proposed using the steering vector formed by the symbol timing offset of the desired signal and interference signals.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2A
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• pp.194-200
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• 2006

A 26.4 GHz phase locked oscillator(PLO) for communication satellite transponder is developed. The PLO consists of fundamental frequency generation module(FFGM) and frequency multiplication part(FMP). The signal of 26.4 GHz is generated through frequency tripling process of 8.8 GHz fundamental frequency. Phase locking technique using sampling phase detector(SPD) is adopted to design the FFGM. The MMIC tripler and amplifier are also designed for the reduction of the size and mass of FMP. The phase noise characteristics are exhibited as -96 dBc/Hz at 10 tHz offset frequency and -105 dBc/Hz at 100 kHz offset frequency, respectively, with the output power over 11 dBm. All performance parameters are complied with the design requirements.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.926-934
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• 2016

In this paper, we designed a compact frequency synthesizer with multi-function for Ka-band seeker. DDS(Direct Digital Synthesizer) is applied to generate various waveform and to cover high-speed frequency sweep. In order to reduce size, waveform generator and frequency up-converter are integrated in one module. Proposed frequency synthesizer provides precise detection and tracking waveform for low and high speed targets. It is observed that fabricated synthesizer performs $0.45{\mu}sec$ frequency switching time and -93.69 dBc/Hz phase noise at offset 1 kHz. The size of the synthesizer is kept within 120 mm width, 120 mm length and 22 mm height.

• Journal of Advanced Navigation Technology
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• v.21 no.4
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• pp.359-364
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• 2017

Since the existing analog village broadcasting system has some technical problems in applying and degradations in performance due to its old equipments, it had been required recently to be changed to a wireless digital system and to develop the standardization. However, it is important to analyze the interference between villages in deploying the efficient digital wireless village broadcasting system. In this paper, simulations for co-channel and adjacent channel interference have been carried out considering digital private mobile radio(dPMR) and digital mobile radio(DMR) systems as a representative mobile radio. These results for frequency reuse and channel separation drawn from the separation distance between villages in co-channel interference and the frequency offset in adjacent interference can be helpful to establish a standard and the testing service in the near future.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.4 s.334
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• pp.1-6
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• 2005

For the low power and low cost transceivers, direct sequence spread spec01m frequency-shift keying (DSSS-FSK) is proposed. A transmitter of the DSSS-FSK signal can be implemented by a simple direct modulation using the phase locked loop. Since the DSSS-FSK signal has negligible power around the carrier frequency, low cost direct conversion receiver can be used. Optimum coherent and semi-coherent correlation detection methods for the DSSS-FSK signal are proposed and analyzed. Segmented semi-coherent correlation detection method is proposed to improve the bit error rate performance in the large carrier frequency offset.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7A
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• pp.947-954
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• 1999

A new low phase noise Dielectric Resonator Parallel Feedback Oscillator(DRPFO) that is proposed in this paper has a simple structure so that it can be fabricated in low cost and with high performance. The proposed DRPFO is in a feedback loop oscillator configuration, which is composed of a low noise amplifier, a power amplifier, a power attenuator, a power divider and a parallel resonator feedback element that consists of a dielectric resonator coupled with two microstrip lines. The measured phase noise of DRPFO was less than -81 dBc/Hz at offset frequency 1 kHz of 10.75 GHz carrier frequency, and the frequency stability of DRPFO was less than $\pm$200 kHz over the temperature range of -40$^{\circ}$C to +60$^{\circ}$C.

• Journal of Broadcast Engineering
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• v.10 no.1 s.26
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• pp.31-42
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• 2005

ATSC DTV system uses FPLL block for acquiring the frequency synchronization. Because the FPLL uses only the pilot signal, the frequency convergence range becomes narrower and it takes a more time to acquire the frequency synchronization as the pilot is distorted. And the spectrum shape around the pilot makes an asymmetric convergence range between the positive frequency offset and the negative frequency offset. This paper proposes the algorithm that requires the Installation of the fitters at the both edges of a VSB spectrum and uses the signal power that passes these filters. The proposed algorithm complements the problems of the asymmetric convergence range and overcomes the performance degradation due to the distortion of a pilot level.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1297-1306
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• 2012

This work presents a 77 GHz radar transmitter for the automotive radar system. An integrated 13 GHz frequency synthesizer fabricated using 130 nm RF CMOS process drives a commercial W-band compound semiconductor monolithic multifunction amplifier(MPA), which includes a frequency multiplier by six to generate 77 GHz transmitting signal. The 13 GHz frequency synthesizer includes a high efficiency injection buffer of 4 dBm output power to drive the MPA. The output power of 77 GHz radar transmitter is higher than 13.99 dBm and the magnitude of the reference spur relative to the carrier is -36.45 dBc. The phase noise is -81 dBc/Hz at 1 MHz offset frequency from the carrier.