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A 1.1V 12b 100MS/s 0.43㎟ ADC based on a low-voltage gain-boosting amplifier in a 45nm CMOS technology (45nm CMOS 공정기술에 최적화된 저전압용 이득-부스팅 증폭기 기반의 1.1V 12b 100MS/s 0.43㎟ ADC)

  • An, Tai-Ji;Park, Jun-Sang;Roh, Ji-Hyun;Lee, Mun-Kyo;Nah, Sun-Phil;Lee, Seung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.7
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    • pp.122-130
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    • 2013
  • This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

Imaging Characteristics of Computed Radiography Systems (CR 시스템의 종류와 I.P 크기에 따른 정량적 영상특성평가)

  • Jung, Ji-Young;Park, Hye-Suk;Cho, Hyo-Min;Lee, Chang-Lae;Nam, So-Ra;Lee, Young-Jin;Kim, Hee-Joung
    • Progress in Medical Physics
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    • v.19 no.1
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    • pp.63-72
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    • 2008
  • With recent advancement of the medical imaging systems and picture archiving and communication system (PACS), installation of digital radiography has been accelerated over past few years. Moreover, Computed Radiography (CR) which was well established for the foundation of digital x-ray imaging systems at low cost was widely used for clinical applications. This study analyzes imaging characteristics for two systems with different pixel sizes through the Modulation Transfer Function (MTF), Noise Power Spectrum (NPS) and Detective Quantum Efficiency (DQE). In addition, influence of radiation dose to the imaging characteristics was also measured by quantitative assessment. A standard beam quality RQA5 based on an international electro-technical commission (IEC) standard was used to perform the x-ray imaging studies. For the results, the spatial resolution based on MTF at 10% for Agfa CR system with I.P size of $8{\times}10$ inches and $14{\times}17$ inches was measured as 3.9 cycles/mm and 2.8 cycles/mm, respectively. The spatial resolution based on MTF at 10% for Fuji CR system with I.P size of $8{\times}10$ inches and $14{\times}17$ inches was measured as 3.4 cycles/mm and 3.2 cycles/mm, respectively. There was difference in the spatial resolution for $14{\times}17$ inches, although radiation dose does not effect to the MTF. The NPS of the Agfa CR system shows similar results for different pixel size between $100{\mu}m$ for $8{\times}10$ inch I.P and $150{\mu}m$ for $14{\times}17$ inch I.P. For both systems, the results show better NPS for increased radiation dose due to increasing number of photons. DQE of the Agfa CR system for $8{\times}10$ inch I.P and $14{\times}17$ inch I.P resulted in 11% and 8.8% at 1.5 cycles/mm, respectively. Both systems show that the higher level of radiation dose would lead to the worse DQE efficiency. Measuring DQE for multiple factors of imaging characteristics plays very important role in determining efficiency of equipment and reducing radiation dose for the patients. In conclusion, the results of this study could be used as a baseline to optimize imaging systems and their imaging characteristics by measuring MTF, NPS, and DQE for different level of radiation dose.

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A development of DS/CDMA MODEM architecture and its implementation (DS/CDMA 모뎀 구조와 ASIC Chip Set 개발)

  • 김제우;박종현;김석중;심복태;이홍직
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.22 no.6
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    • pp.1210-1230
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    • 1997
  • In this paper, we suggest an architecture of DS/CDMA tranceiver composed of one pilot channel used as reference and multiple traffic channels. The pilot channel-an unmodulated PN code-is used as the reference signal for synchronization of PN code and data demondulation. The coherent demodulation architecture is also exploited for the reverse link as well as for the forward link. Here are the characteristics of the suggested DS/CDMA system. First, we suggest an interlaced quadrature spreading(IQS) method. In this method, the PN coe for I-phase 1st channel is used for Q-phase 2nd channels and the PN code for Q-phase 1st channel is used for I-phase 2nd channel, and so on-which is quite different from the eisting spreading schemes of DS/CDMA systems, such as IS-95 digital CDMA cellular or W-CDMA for PCS. By doing IQS spreading, we can drastically reduce the zero crossing rate of the RF signals. Second, we introduce an adaptive threshold setting for the synchronization of PN code, an initial acquistion method that uses a single PN code generator and reduces the acquistion time by a half compared the existing ones, and exploit the state machines to reduce the reacquistion time Third, various kinds of functions, such as automatic frequency control(AFC), automatic level control(ALC), bit-error-rate(BER) estimator, and spectral shaping for reducing the adjacent channel interference, are introduced to improve the system performance. Fourth, we designed and implemented the DS/CDMA MODEM to be used for variable transmission rate applications-from 16Kbps to 1.024Mbps. We developed and confirmed the DS/CDMA MODEM architecture through mathematical analysis and various kind of simulations. The ASIC design was done using VHDL coding and synthesis. To cope with several different kinds of applications, we developed transmitter and receiver ASICs separately. While a single transmitter or receiver ASC contains three channels (one for the pilot and the others for the traffic channels), by combining several transmitter ASICs, we can expand the number of channels up to 64. The ASICs are now under use for implementing a line-of-sight (LOS) radio equipment.

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